A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation

This research introduces a novel defense mechanism against hardware security threats, specifically targeting SAT attacks on Integrated Circuits (ICs). By leveraging neural networks, the proposed method translates SAT-prone clauses into SAT-hard clauses, significantly enhancing the security of logic obfuscation techniques with minimal performance overhead.

Research Problem

The increasing reliance on offshore foundries for IC fabrication has heightened the risk of hardware security threats, including reverse engineering and intellectual property theft. Traditional logic obfuscation techniques are vulnerable to SAT attacks, which can decrypt the obfuscated circuits in a short time. This research aims to develop a robust defense mechanism that mitigates SAT attacks while maintaining low power, performance, and area (PPA) overheads.

Methods or Approach

Neural Network-Based SAT-Hard Clause Generator
Message Passing Neural Network (MPNN)
LSTM Network
Integration with Existing Circuits

Key Findings

Successfully defends against multiple state-of-the-art SAT attacks.
Empirical evaluations on ISCAS'85 benchmarks demonstrate effectiveness.
Minimal PPA overheads while preserving original functionality.

Impact and Future Applications

Enhanced Security: Provides a robust defense mechanism against SAT attacks, protecting ICs from reverse engineering and IP theft.
Low Overheads: Achieves high security with minimal impact on power, performance, and area.
Scalability: Can be applied to various hardware security scenarios, making it a versatile solution for the semiconductor industry.
Future Applications: Advanced hardware security and integration with emerging technologies.

Circuit Topology-aware Vaccination-based Hardware Trojan Detection

This research introduces a novel approach for detecting Hardware Trojans (HTs) in integrated circuits (ICs) by considering both circuit topology and behavior. The proposed method combines structural features, such as node types and connectivity, with behavioral information derived from abnormal conditions (analogous to vaccination) to detect HTs effectively using a Graph Neural Network (GNN) model.

Research Problem

HTs pose significant security threats to modern ICs by performing unauthorized actions like leaking sensitive information, executing unauthorized commands, or reducing IC lifespan. Traditional detection methods, such as functional and structural verification, are ineffective for detecting stealthy HTs due to rare triggers and specific design limitations. This research addresses these challenges by introducing a circuit topology-aware HT detection method that combines structural and behavioral analysis.

Methods or Approach

Graph Neural Network (GNN) for HT Detection
Graph Convolution Network (GCN) for feature extraction
Vaccination-based approach using overclocking and bit-flip pattern analysis
Extraction of circuit topology features like node degree, gate types, and connectivity
Combining structural features with behavioral data for a comprehensive HT detection model

Key Findings

The proposed GNN model achieves around 93.15% accuracy in detecting HTs across various benchmarks.
The model effectively learns the distribution of Trojan-inserted features and differentiates them from HT-free designs without requiring a golden reference IC.
Combining graph-level and behavioral features provides a robust method for distinguishing between Trojan-inserted and HT-free ICs.

Impact and Future Applications

Improved HT detection across different IC designs without needing a golden reference IC.
Potential for scalability in various hardware security applications, such as IoT security and secure IC manufacturing.
Integration with advanced machine learning techniques for enhanced performance.

Automated Supervised Topic Modeling Framework for Hardware Weaknesses

This research presents a Machine Learning-based framework for vulnerability and impact vector classification, focusing on hardware vulnerabilities in the IoT domain. The proposed framework utilizes an Ontology-driven Storytelling Framework (OSF) and updates the ontology in an automated manner, helping to identify similar patterns of vulnerabilities over time and mitigating their impacts.

Research Problem

The increasing complexity of modern computing systems has resulted in a growth of security vulnerabilities, making them appealing targets for evolving security threats. Traditional methods for analyzing these vulnerabilities often focus on software, neglecting the unique challenges posed by hardware vulnerabilities, especially in IoT devices. This research addresses the need for effective tools to identify, analyze, and mitigate hardware vulnerabilities over time.

Methods or Approach

Ontology-driven Storytelling Framework (OSF) for dynamic vulnerability analysis
Use of Natural Language Processing (NLP) and Machine Learning (ML) techniques to extract meaningful insights from vulnerability databases
Integration of data from National Vulnerability Database (NVD) and Common Weakness Enumeration (CWE) for comprehensive analysis
Automatic entity extraction and ontology updating based on new data

Key Findings

The OSF framework can dynamically identify and analyze hardware vulnerabilities over time, providing a storytelling framework for understanding trends and relationships between vulnerabilities.
The proposed method effectively integrates data from multiple sources, providing a holistic view of hardware weaknesses in the IoT domain.
Provides an interactive Graphical User Interface (GUI) for meaningful visualization and analysis of vulnerability trends and impacts.

Impact and Future Applications

Improved understanding of hardware vulnerabilities and their impacts over time, aiding in the development of more secure IoT devices.
Potential for integration with advanced machine learning models to enhance prediction and prevention of future vulnerabilities.
Scalability for use in various domains where hardware vulnerabilities pose significant security threats.