Hardware projects

  1. Design entry method (e.g., VHDL, Verilog, schematic), target implementation (e.g., Xilinx or Altera FPGA, ASIC semi-custom standard-cell circuit), CAD tools used to specify, implement, and verify the design (e.g., Xilinx Foundation Series 1.4, Altera MAX+PLUSII, Mentor Graphics, Cadence).
  2. Additional libraries of basic digital circuits required (e.g., Xilinx LogiBlox, MOSIS library).
  3. Detailed specification of the input and output of the circuit(s).
  4. Brief description of the function performed by the circuit(s), including any specific references to standards and detailed descriptions of algorithms in the literature.
  5. Procedures for testing the functionality and performance of the circuit(s) at the gate level, including a. The simulator in use. b. The source of test vectors. c. The format of input stimuli (e.g., VHDL test bench, simulator script). d. Performance parameters to be determined by simulation (e.g., throughput, key setup time, time to encrypt one block, time to switch keys). e. Parameters to be determined using the implementation tools (e.g., number of CLBs in the FPGA implementation, minimum size FPGA device able to hold the device, area of the circuit in the standard-cell implementation).
  6. Plan of simulation experiments to be performed using the circuit(s).
  7. Time schedule, including intermediate goals to be achieved by the dates of progress reports (March 25, April 8, April 22).
  8. A list of possible areas, where the specification can change depending on the progress of the project.
  9. Anything else you consider important.