About Me

I am a Ph.D student in the ECE Department of George Mason University. I am working with Dr. Jens-Peter Kaps as a part of Cryptographic Engineering Research Group (CERG). For more details about my publications and research, please use the links on this page

Contact Information

3100 Engineering Building, George Mason University ECE Department, CERG 4400 University Drive, MS 1G5 Fairfax, VA 22030

Office: Engineering Building , Room 3224 Phone (lab): 703-993-1561 E-Mail: rvelegal'at'gmu.edu

News:

Sept 24-26, 2013:	Attended The 1st International Cryptographic Module Conference, ICMC 2013 at Gaithersburg, Maryland, to present my work titled "Electro Magnetic Fault Injection in Practice."
June-24-2013:	My work titled "Towards a Flexible, Opensource BOard for Side-channel analysis (FOBOS)" has been accepted for presentation at CryptArchi 2013.
May-27-2013:	My work titled "Glitch detection in hardware implementations on FPGAs using delay based sampling techniques" has been accepted for presentation at DSD 2013.
Feb-04-2013:	From Feb-04-2013 to Aug-16-2013, I will be working as a Research Intern at Riscure NA Inc., San Francisco, CA.
Oct-2nd-2012:	Nist announces "Keccak as the winner of SHA-3 Cryptographic Hash Algorithm Competition.". Congratulations to the Keccak team.
May 3rd-4th, 2012:	My work-in-progress titled "Introducing FOBOS: Flexible Open-source BOard for Side-channel analysis" has been accepted for presentation at Third International Workshop on Constructive Side-Channel Analysis and Secure Design COSADE 2012, Darmstadt, Germany, May 03-04, 2012.
March 17th-18th, 2012:	CERG organized SHARCS 2012 - Special-Purpose Hardware for Attacking Cryptographic Systems workshop held in the Washington Marriott Hotel on March 17-18, 2012.
Feb 16th-17th, 2012:	Attended 2nd NIST meeting at George Mason Unversity about NIST ARRA sponsered project review, titled "Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software". We had exciting discussion about the basis behind the selection of new SHA3. It was a good learning experience.
Dec-6th-2011:	Sucessfully defended my Ph.D proposal.
Oct-18th-2011:	Attended The second annual Symposium on Business Globalization: Managing the Cyber Security Challenge held at Washington D.C, The Ritz-Carlton. Dr. Fareed Zakaria gave an intresting keynote presentation.
May-25th-2011:	My work titled "Improving Security of SDDL Designs Through Interleaved Placement on Xilinx FPGAs" has been accepted for presentation at FPL 2011.
Nov 8th-9th, 2010:	Attended NIST meeting at George Mason Unversity about NIST ARRA sponsered project, titled "Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software", which is a joint work with GMU, VT and UIC.
Oct-4th-2010:	My work with Shaunak Shah titled "Investigation of DPA Resistance of Block RAMs in FPGAs" has been accepted for presentation at ReConFig 2010, to be held in Cancun, Mexico, December 5-7, 2010.
Sept-29th-2010:	My work titled "Techniques to enable the use of Block RAMs on FPGAs with Dynamic and Differential Logic" has been accepted for presentation at the IEEE International Conference on Electronics, Circuits, and Systems, to be held in Athens, Greece, December 12-15, 2010.
Aug-28-2010:	Passed my Ph.D Qualifying Exam.
May 2nd-4th, 2010:	Attended The 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2101 at Charlotte, North Carolina, to present my work titled "DPA resistant AES on FPGA using partial DDL."
31-Aug-2009:	Started my Ph.D in ECE at George Mason University.
27-July-2009:	Sucessfully defended my Master's Thesis titled "Securing light weight cryptographic implementations on FPGAs using dual rail with pre-charge logic."
22-May-2009:	My work titled "DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs" was accepted as oral presenation at FPL 2009.