Library IEEE;
use ieee.std_logic_1164.all;

entity multiplier_impl is
	port(
		clock, reset: in std_logic;

		inputA, inputB: in std_logic_vector(15 downto 0);
		output: out std_logic_vector(15 downto 0)
	);
end multiplier_impl;

architecture implementation of multiplier_impl is

	component multiplier
		generic(
			inputs_size: integer;
			output_size: integer;
			pipeline: integer
			-- pipeline gives number of pipeline stages
			-- 1 = combinational circuit
		);
		port(
			clock, reset: in std_logic;
	
			inputA, inputB: in std_logic_vector(inputs_size-1 downto 0);
			output: out std_logic_vector(output_size-1 downto 0)
		);
	end component;

	signal inA_reg, inB_reg: std_logic_vector(15 downto 0);
	signal result: std_logic_vector(15 downto 0);

begin

	U_input_register: process(clock, reset)
	begin
		if(reset = '1') then
			inA_reg <= (others => '0');
			inB_reg <= (others => '0');
		elsif(clock = '1' and clock'event) then
			inA_reg <= inputA;
			inB_reg <= inputB;
		end if;
	end process;

	U_multiplier: multiplier
		generic map(
			inputs_size => 16,
			output_size => 16,
			pipeline => 3
		)
		port map(
			clock => clock,
			reset => reset,

			inputA => inA_reg,
			inputB => inB_reg,
			output => result
		);

	U_output_register: process(clock, reset)
	begin
		if(reset = '1') then
			output <= (others => '0');
		elsif(clock = '1' and clock'event) then
			output <= result;
		end if;
	end process;

end implementation;