Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
	generic(
		inputs_size: integer;
		output_size: integer;
		pipeline: integer
		-- pipeline gives number of pipeline stages
		-- 1 = combinational circuit
	);
	port(
		clock, reset: in std_logic;

		inputA, inputB: in std_logic_vector(inputs_size-1 downto 0);
		output: out std_logic_vector(output_size-1 downto 0)
	);
end multiplier;

architecture behavior of multiplier is

	signal result: std_logic_vector((2*inputs_size)-1 downto 0);
	type pipe is array(pipeline-1 downto 0) of std_logic_vector(output_size-1 downto 0);
	signal pipeline_regs: pipe;

begin
----- Multiplication --------

	result <= inputA * inputB;

----- Pipeline stages -------

	pipeline_regs(pipeline-1) <= result(output_size-1 downto 0);

	U_pipeline: for i in pipeline-2 downto 0 generate
		U_register: process(clock, reset)
		begin
			if(reset = '1') then
				pipeline_regs(i) <= (others => '0');
			elsif(clock = '1' and clock'event) then
				pipeline_regs(i) <= pipeline_regs(i+1);
			end if;
		end process;
	end generate;

	output <= pipeline_regs(0);

end behavior;