Homework 5
due Wednesday, April 22, 4:00 PM (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Reading
Read the following paper in Blackboard:
J. Tierney, C. Rader, B. Gold, "A Digital Frequency Synthesizer," IEEE Trans. of Audio and Electroacoustics, vol. 19, no. 1, pp. 48 - 57, March 1971.
Read the following sections of the textbook "VLSI Digital Signal Processing Systems" by K. Parhi:
Chapter 4, Retiming
Problems
1) VHDL
Part 1: Coding
Code the simple DDFS shown here. Select a frequency control word k. Then reset the system (time n=0). After reset, the DDFS should produce the values cos(2pi/N* (nk mod N)) and sin(2pi/N* (nk mod N)), where n is the time index starting from n=0. Remember, an L-bit unsigned adder without carryout automatically performs mod N addition, where N=2^L. Use the following entity declaration:
entity homework5 is
port (
clk: in std_logic;
rst: in std_logic; -- active high synchronous reset
k: in std_logic_vector(9-1 downto 0); -- frequency control word U9.0
cosout, sinout: out std_logic_vector(12-1 downto 0) -- outputs S12.11
);
end homework5;
You will need to use your knowledge of Matlab to produce the S12.11-bit values which should fill the cos/sin ROM. Create a script called generate_table.m which will do this. Note that cos(0) = sin(pi/2) = 1 exactly, which will not fit in an S12.11 value. Thus, use the binary value 0.11111111111 to approximate the value 1. It is up to you to use to use truncation or rounding when going from a floating point sine and cosine to a S12.11 sine and cosine.
Part 2: Testbench
Create a testbench which tests your circuit for 512 samples for the value of k=1. Save your cos and sin outputs to files called cosout_k1.dat and sinout_k1.dat. Repeat the simulation for the value of k=99. Save your cos and sin outputs to files called cosout_k99.dat and sinout_k99.dat.
Load these binary results in Matlab, convert them to decimal values, and plot them (i.e. plot the cosine and sine waves so they go between the decimal value of -1 and 1) using a script you create called plot_waves.m. Save your plots in JPG format as cosout_k1.jpg, sinout_k1.jpg, cosout_k99.jpg, and sinout_k99.jpg.
Part 3: FPGA Synthesis
Synthesize the design on the smallest Virtex4 device you can fit it in. You should not do implementation.
- Perform synthesis for Virtex 4.
- Perform post-synthesis simulation if using Aldec (post-translate simulation if using Xilinx/Modelsim) at some reasonable clock frequency (i.e. 10 MHz). Save your file outputs as cosout_k1_postsyn.dat, sinout_k1_postsyn.dat, cosout_k99_postsyn.dat, and sinout_k99_postsyn.dat. Plot your results in Matlab and save your plots as cosout_k1_postsyn.jpg, sinout_k1_postsyn.jpg, cosout_k99_postsyn.jpg, and sinout_k99_postsyn.jpg.
What to Turn In
Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below. Submit one zip file with the following:
- All VHDL source codes, including VHDL testbench
- Matlab files: generate_table.m, plot_waves.m, any other Matlab files.
- All behavioral test files, including: cos/sinout_k1.dat, cos/sinout_k99.dat, cos/sinout_k1.jpg, cos/sinout_k99.jpg
- Waveforms from behavioral simulation (in .awf format for Active HDL or .wlf format for ModelSim). You can choose to submit either the k=1 or k=99 waveform.
- All post-synthesis test files, including: cos/sinout_k1_postsyn.dat, cos/sinout_k99_postsyn.dat, cos/sinout_k1_postsyn.jpg, cos/sinout_k99_postsyn.jpg
- Waveforms from simulation post-synthesis (in .awf format for Active HDL) or post-translate (in .wlf format for ModelSim). You can choose to submit either the k=1 or k=99 waveform.
- Synthesis report
- A short report called homework5_results.txt which answers:
- Were you able to produce the behavioral cosine and sine waves correctly for k=1 and k=99? If not, explain.
- Were you able to produce the post-synthesis cosine and sine waves correctly for k=1 and k=99? If not, explain.
- Results after synthesis: #slices, #flip-flops, #LUTs, #block RAMs, #DSP48s, maximum clock frequency, minimum period. If your synthesis tool only gives slices instead of LUTs (or vice-versa) after synthesis, just note this.
- Discuss any problems encountered.
2) Handwritten Problems
You can scan in these problems and submit them via Blackboard, or turn them in at the beginning of class on Wednesday, April 22.
Parhi, Section 4.6, Problem 1. Do all parts of the problem.
Parhi, Section 4.6, Problem 2. In addition to parts (a), (b), and (c), also add an additional part:
(d) Retime this DFG using the equations and methodology in 4.4.2 (Retiming for Clock Period Minimization). Show all work. The Matlab code for the Floyd-Warshall algorithm and some Floyd-Warshall examples have been put in Blackboard in the folder "Matlab Code."
Parhi, Section 4.6, Problem 3. Do all parts of the problem. NOTE: If the iteration bound T is not an integer, then after retiming make your critical path be equal to ceil(T), where ceil() is the next highest integer.