Homework 4
due Wednesday, March 18, 4:30 PM (NO LATE HOMEWORK ACCEPTED)
Submit at beginning of class on March 18. If you will not be in class, scan in your assignment and email it to me. Your email must be received by the deadline.
Reading
Read the following sections of the textbook "VLSI Digital Signal Processing Systems" by K. Parhi:
Chapter 2, Iteration Bound (sections 2.1 - 2.4, and section 2.6)
Chapter 10, Pipelined and Parallel Recursive and Adaptive Filters (sections 10.1 - 10.4)
Problems
Section 2.7, Problem 1.
Section 2.7, Problem 3. Hint: In calculating iteration bound you can completely ignore the feedforward paths.
Section 10.10, Problem 1. No need to draw these circuits, just their equations. Hint: Equation (10.30) is useful.
Section 10.10, Problem 2. You are implementing a circuit for M=2. Assume that Tmult = 4 u.t. and Tadd = 2 u.t., and that Tmult can be divided into even sections for pipelining purposes. Complete all parts of the question, including drawing the complete structure. For the feedforward section, you can use whatever structure you prefer and pipeline however you feel necessary--however do this as efficiently as possible.
In addition, for this problem also answer the questions below:
1) What is the critical path of your circuit?
2) What is the iteration bound of your circuit?
3) Does the iteration bound equal the critical path? Why or why not?