HW3 FAQs

1) If you need more information on the DSP48 block generics, go to http://www.xilinx.com/itp/xilinx8/books/docs/v4ldl/v4ldl.pdf. Pages 87-94 have more information on the DSP48 instantiation and the generic values. (This PDF is actually linked from the original XtremeDSP for Virtex-4 FPGAs on page 17).

2) In the Xilinx design example code, they use the value CE, which they connect to all the clock enables and other various enables in the DSP48 block. So in their code CE can be interpreted as "chip" enable. You can keep all clock enables and other enables high (i.e. if you use their madd modules, you can keep CE high) but just make sure you know what each of these enables are doing.

3) If you are using the Xilinx design example code and are having problems with generic "SIM_X_INPUT" not being an entity port, comment out this generic, i.e. comment out the line: SIM_X_INPUT : string := "GENERATE_X_ONLY"

4) If you are using the Xilinx design example code, you may be having problems with post-synthesis simulation; in other words your DSP48 blocks may be configured incorrectly. This may be due to using synthesis compiler directives.

To fix this, in madd_first.vhd, madd_last.vhd, and madd.vhd around the code where the DSP48 component is declared, COMPLETELY DELETE the lines which say "--synthesis translate_off" and "-- synthesis translate_on". Depending on how you set up your synthesis tool, these are compiler directives which will tell the tool to ignore the set up of the generics for the DSP48. This will cause the post-synthesis DSP48 simulation to be incorrect because the DSP48 blocks are not configured correctly (they are set to some default value). 

Then you should add a GENERIC MAP section when you instantiate the DSP48; map all the generics to the values which are given in the component declaration section (these will be different for madd_first.vhd, madd_last.vhd, and madd.vhd). Actually, you only need to add the GENERIC MAP section for Synplify, not for XST, but to be safe add it for XST as well.

5) Symmetric Rounding. Looking at the figure 4-9 of the Xtreme DSP user guide, we want symmetric rounding. That is we insert a rounding vector (such as 0000...000111...11111111) into the C port of the DSP48. 

For a positive number x, we add x + rounding_vector + 1 LSB 
For a negative number x, we add x + rounding_vector 

This performs symmetric rounding. The addition of the extra LSB for positive numbers can be done by setting the carryinsel 2-bit port on the last DSP48 block to '01' as shown in the figure 4-9. Go to page 32 of the PDF (Table 1-8). In the table when the carryinsel = '01' then ~P[47] (which is the inversion of the MSB) is used as the carryin. In other words, when P is positive an LSB is added, when P is negative it is left alone.

6) In the Matlab, the only lines that need to be changed from floor(x + 0.5) to round(x) are lines 61 and 64. Actually, for this project, only line 64 really needs to be changed.