Homework 2

due Friday, February 13, 4:00 pm
due Wednesday, February 18, 4:00 PM (NO LATE HOMEWORK ACCEPTED)

submission using Blackboard


Problem

Part 1: Coding

The following code was used to generate the example on slides 50-61 of Lecture 2. You will need the "signal processing toolbox" to run this code:

fir_filter.m
print_vector.m

In the code, the parameters are set in default for M = 4 coefficients, N1=N2=N3=16 total bits, L1=L2=L3=15 fractional bits, quant_type = 1 (rounding), many_quant = 0 (one quantizer). In this homework you will slightly modify the code and create two new filters:

homework2_onequant: M = 12 coefficients, N1=N2=N3=12 totals bits, L1=L2=L3=11 fractional bits, quant_type = 1 (round to nearest), many_quant = 0 (i.e. one quantizer after final adder)

homework2_manyquant: M = 12 coefficients, N1=N2=N3=12 totals bits, L1=L2=L3=11 fractional bits, quant_type = 1 (round to nearest), many_quant = 1 (i.e. 12 quantizers, one after each multiplier)

Develop the complete VHDL code including library declaration, entity declaration, and architecture for these two circuits. In your VHDL code be sure to insert an input register and output register (for timing purposes), as shown here.

Regarding the MSBs and LSBs, assume the word growth quantization is the same as those shown in slides 50-61 of Lecture 2. That is, remove MSBs and quantize LSBs assuming the final value of y (SN.L) is the same size as the input value x (SN.L). See lecture slides 50-61 for more details. Your Matlab and VHDL should do round to nearest (not truncation).

It is recommended you use the std_logic_signed package. Use whatever coding technique (dataflow, behavioral, structural) you prefer. IMPORTANT: Your code should work for ANY generic integer values of N and L (assuming N>L, L>1). Be sure to use std_logic or std_logic_vector for all entity input and output ports, not integer, signed, or unsigned. Use "in" or "out" for port types; do not use "buffer".

Use the following entity declaration. Assume N and L are generic, but in VHDL assume the number of coefficients (i.e. M) is fixed at 12 so it is not generic:

entity homework2_onequant [or homework2_manyquant] is
  generic (
    N: integer:=12; -- N = total number of bits for N1, N2, N3 (assuming N1=N2=N3)
    L: integer:=11); -- L = number of fractional for L1, L2, L3 (assuming L1=L2=L3)
  port (
    clk: in std_logic;
    rstn: in std_logic; -- assume all registers have asynchronous active low reset
    x: in std_logic_vector(N-1 downto 0); -- SN.L number
    y: out std_logic_vector(N-1 downto 0); -- SN.L number
    h0: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(0)
    h1: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(1)
    h2: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(2)
    h3: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(3)
    h4: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(4)
    h5: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(5)
    h6: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(6)
    h7: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(7)
    h8: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(8)
    h9: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(9)
    h10: in std_logic_vector(N-1 downto 0); -- SN.L number, coeff h(10)
    h11: in std_logic_vector(N-1 downto 0)); -- SN.L number, coeff h(11)
end homework2_onequant [or homework2_manyquant];


Part 2: Testbench

Create test vectors in Matlab by changing the Matlab script to the appropriate parameters and producing vectors d_in.dat, d_out.dat, and h.dat. Based on the script, d_in.dat and d_out.dat should both be 100 samples each.

Create a VHDL testbench which tests your design for N=12, L=11 and matches the test vectors from Matlab. Your testbench should first load in the h.dat file and assign the coefficients to h0 through h11; these will remain the same throughout the entire simulation. Next, reset the circuit and then run through all inputs in the d_in.dat file. The inputs should change at the negative edge of the clock.

As you are running the code, at the appropriate time, check the first VHDL output with the Matlab output from d_out.dat; if this first output is exactly the same, print "match" (and a carriage return) in a file called verify.dat; if the output does not exactly match, print "error" in the verify.dat file. Do this for all 100 output samples. If your VHDL and Matlab match, then the verify.dat file should be a 100-line file with each line having the word "match" in it. Help with VHDL file I/O can be found here or slides 67-81 of this file.

Save the waveforms from simulation (i.e. in .awf format for Active HDL or .wlf format for ModelSim) and submit all of them. You should perform functional simulation and post-synthesis (or post-translate) simulation. There is no need to do post-place-and-route simulation.

Part 3: FPGA Synthesis

For each of the two designs, synthesize the design for N=12, L=11 on the smallest Virtex4 device you can fit it in (you may need to pick one with a lot of pins since you will have 150+ pins required--though this really only matters for implementation). You should not do implementation. What to Turn In

Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below. Submit 3 files:

  • Submit a zip file called homework2_onequant.zip. This zip file should contain:
  • Submit a zip file called homework2_manyquant.zip. This zip file should contain:
  • Submit a short report called yourname_homework2_report.txt (or .doc or .pdf). The report should have the exact numbering below: