To clarify:

-After multiplication remove MSBs such that the number of integer bits after the multiplication is the same as the number of integer bits for the multiplication input (i.e. integer bits = N-L). For example, N=6, L=3. If you have S6.3 x S6.3 = S12.6, then remove 3 MSBs until the result is S9.6. 

-Then truncate this value until the resulting wordlength is the same as the input wordlength (i.e. total bits = SN.L). For example, truncate the last three bits of the S9.6 value to make an S6.3 value.

It seems if you remove too many MSBs you will get underflow/overflow and will lose information. However, the reason this works is a neat property in two's complement that we will discuss next lecture.
Say you have the equation: Y = A * B + C * D

Assume A, B, C, and D are S4.2 values, so they range from -2 <= number < 2

Say:
A = 01.10 = 1.5
B = 10.00 = -2
C = 01.10 = 1.5
D = 01.00 = 1

A x B:
Result of multiplication is an S8.4 number: A x B = 1101.0000 = -3 Remove two MSBs to make an S6.4 number = 01.0000 = 1 --> apparent ERROR, went from a negative number to a positive number!
Truncate two LSBs to make an S4.2 number = 01.00 = 1 (truncating only introduces some fixed error, in this case I created the example to not have error)

C x D:
Result of multiplication is an S8.4 number: C x D = 0001.1000 = 1.5 Remove two MSBs to make an S6.4 number = 01.1000 = 1.5 Truncate two LSBs to make an S4.2 number = 01.10 = 1.5 (truncating only introduces some fixed error, in this case I created the example to not have error)

Now add A x B + C x D while IGNORING overflow to produce an S4.2 number:

01.00 + 01.10 = 10.10 --> apparent ERROR, adding two positive numbers should produce a positive number not a negative number!

However, 10.10 = -1.5, which is the correct answer for Y, since (1.5 x -2 + 1.5 x 1) = (-3 + 1.5) = -1.5! The reason this works is that the final result for Y is in the range of S4.2. In general if you have a chain of two's complement multiplications/additions with an output wordlength SN.L, and you can guarantee the final result will be in the output wordlength's allowable range, then all intermediate overflow/underflows will cancel out and the answer will be correct--this is due to the two's complement modulo property. More on this in next week's lecture.

Of course in HW#1 we will get overflow due to the way I constructed the problem--this homework is not a "true" digital filter. It is an artificially simplified DSP-like structure designed only to get everyone up-to-speed on coding in VHDL and implementing in the FPGA CAD tools.