Homework 1
due Friday, January 30, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Information about Blackboard
All students with a GMU email account already have a Blackboard account automatically created for them. Use your GMU email username and password to access Blackboard.
Reading
No official reading. If you need a refresher on VHDL you can look over last semester's ECE 545 class here or review the book: Volnei A. Pedroni, Circuit Design with VHDL.
Problem
Part 1: Coding
Develop the complete VHDL code including library declaration, entity declaration, and architecture for the circuit shown here.
Here is a note of clarification on how to take away MSBs and truncate LSBs: note of clarification.
It is recommended you use the std_logic_signed package. Use whatever coding technique (dataflow, behavioral, structural) you prefer. IMPORTANT: Your code should work for ANY generic integer values of N, L, and M (assuming N>L, L>1 and M>1). Be sure to use std_logic or std_logic_vector for all entity input and output ports, not integer, signed, or unsigned. Use "in" or "out" for port types; do not use "buffer".
Use the following entity declaration:
entity homework1 is
generic (
N: integer:=8; -- N = total number of bits
L: integer:=7; -- L = number of fractional bits
M: integer:=9); -- M = number of stages
port (
clk: in std_logic;
rstn: in std_logic;
x: in std_logic_vector(N-1 downto 0); -- SN.L number
y: out std_logic_vector(N-1 downto 0)); -- SN.L number
end homework1;
Part 2: Testbench
Create a testbench which tests your design for N=8, L=7, and M=9. Your testbench should first reset the circuit and then run through all inputs from x="00000000", "00000001", ... until you reach "11111111". The input x should transition every clock period on the negative edge of the clock. Once x reaches "11111111", you can stop the simulation.
Save the waveforms from simulation (i.e. in .awf format for Active HDL or .wlf format for ModelSim) and submit all of them using Blackboard. You should perform functional simulation, post-synthesis (or post-translate) simulation, and post-place-and-route simulation.
Part 3: FPGA Synthesis and Implementation
Synthesize and implement the design for N=8, L=7, and M=9 on the smallest Virtex4 device you can fit it in. Specifically, you should:
- Perform synthesis for Virtex 4. Assume N=8, L=7, and M=9.
- Perform post-synthesis simulation if using Aldec (post-translate simulation if using Xilinx/Modelsim) at some reasonable clock frequency (i.e. 10 MHz).
- Perform implementation targeting the smallest device of the Xilinx Virtex 4 family
- Perform post-place-and-route timing simulation at some reasonable clock frequency (i.e. 10 MHz)
- Perform static timing analysis
What to Turn In
Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below.
- All source codes, including test bench
- Create a text file called homework1_results.txt. In the text file, give a short summary of:
- Results after synthesis: #slices, #flip-flops, #LUTs, #block RAMs, #DSP48s, maximum clock frequency, minimum period. If your synthesis tool only gives slices instead of LUTs (or vice-versa) after synthesis, just note this in your text file.
- Results after implementation: #slices, #flip-flops, #LUTs, #block RAMs, #DSP48s, maximum clock frequency, minimum period
- Synthesis report
- Full implementation report(s): translate, map, place, route
- Static timing analysis report
- Waveforms from simulation before synthesis (in .awf format for Active HDL or .wlf format for ModelSim)
- Waveforms from simulation post-synthesis (in .awf format for Active HDL) or post-translate (in .wlf format for ModelSim)
- Waveforms from simulation post place-and-route which includes timing (in .awf format for Active HDL or .wlf format for ModelSim)