LIBRARY ieee ;
   USE ieee.std_logic_1164.all ;

   ENTITY regne IS
      GENERIC ( n : INTEGER := 32 ) ;
		PORT (	R 		: IN 	STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
				rst 	: IN 	STD_LOGIC ;	
				set 	: IN 	STD_LOGIC ;
				E 		: IN 	STD_LOGIC ;
				clk 	: IN 	STD_LOGIC ;
				Q 		: OUT 	STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
   END regne ;	
   
   ARCHITECTURE Behavior OF regne IS	
	BEGIN
		PROCESS (clk)
			BEGIN
				IF (clk'EVENT AND clk = '1' ) THEN	 
				    IF rst = '1' THEN 
					   Q <= (OTHERS => '0');
					ELSIF set = '1' THEN 
					   Q <= (OTHERS => '1');
					ELSIF E = '1' THEN
						Q <= R ;
					END IF ;
				END IF;
		END PROCESS ;
	END Behavior ;