library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;  

use ieee.STD_LOGIC_TEXTIO.all;
use std.textio.all;


entity minmaxavg_tb is
		generic(
		n : INTEGER := 32;
		k : INTEGER := 8;
		m : INTEGER := 3 );
end minmaxavg_tb;

architecture TB_ARCHITECTURE of minmaxavg_tb is

	component minmaxavg
	generic(				-- comment this line out for post-synthesis or post-place-and-route simulation!!!
		n : INTEGER := 32;	-- comment this line out for post-synthesis or post-place-and-route simulation!!!
		k : INTEGER := 8;	-- comment this line out for post-synthesis or post-place-and-route simulation!!!
		m : INTEGER := 3);	-- comment this line out for post-synthesis or post-place-and-route simulation!!!
	port(
		clk : in std_logic;
		reset : in std_logic;
		START : in std_logic;
		write : in std_logic;
		read : in std_logic;
		in_data : in std_logic_vector(n-1 downto 0);
		in_addr : in std_logic_vector(m-1 downto 0);
		out_addr : in std_logic_vector(1 downto 0);
		DONE : out std_logic;
		out_data : out std_logic_vector(n-1 downto 0));
	end component;


	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic := '0';
	signal reset : std_logic;
	signal in_data : std_logic_vector(n-1 downto 0);
	signal in_addr : std_logic_vector(m-1 downto 0);
	signal write : std_logic;
	signal START : std_logic;
	signal out_addr : std_logic_vector(1 downto 0);
	signal read : std_logic;	
	
	-- Observed signals - signals mapped to the output ports of tested entity
	signal DONE : std_logic;
	signal out_data : std_logic_vector((n-1) downto 0);	 
	
    file in_vectorFile : TEXT open read_mode is "inputs.txt"; -- input file should be where source VHDL code is located
    file out_vectorFile : TEXT open write_mode is "outputs.txt"; -- this file will be generated by the simulator
	
	constant ClkPeriod: time := 20 ns;

begin
	UUT  : minmaxavg
	generic map(	   -- comment this line out for post-synthesis or post-place-and-route simulation!!!
		n => n,		   -- comment this line out for post-synthesis or post-place-and-route simulation!!!
		k => k,		   -- comment this line out for post-synthesis or post-place-and-route simulation!!!
		m => m)		   -- comment this line out for post-synthesis or post-place-and-route simulation!!!
	port map(
		clk => clk,
		reset => reset,
		START => START,
		write => write,
		read => read,
		in_data => in_data,
		in_addr => in_addr,
		out_addr => out_addr,
		DONE => DONE,
		out_data => out_data
	);


  	readVec: process

	    variable VectorLine: line;
	    variable VectorValid: boolean;	  
		variable input_vector: STD_LOGIC_VECTOR(n-1 downto 0);
		variable addr_counter: STD_LOGIC_VECTOR(m-1 downto 0);
		
		begin  	
			
		reset <= '1';
		START <= '0';
		addr_counter := (OTHERS => '1'); 
		in_addr <= (OTHERS => '0'); 
		in_data <= (OTHERS => '0');
		out_addr <= "00"; 
		write <= '0';
		read <= '0';
		
		wait for 4*ClkPeriod;
	
		reset <= '0';
		write <= '1'; 
		
	    while not endfile (in_vectorFile) loop
	      readline(in_vectorFile, VectorLine);	-- read from input file to a line variable
	      hread(VectorLine, input_vector); -- put line variable into a std_logic_vector variable
	
	      in_data <=  input_vector ;
		  addr_counter := addr_counter + 1;	  
		  in_addr <= addr_counter ;
	
	      wait for ClkPeriod;	
		  
	    end loop; 
		
		write <= '0';  
		
		wait until clk'event and clk='0';  
		START <= '1';
		wait for ClkPeriod ;
		START <= '0';	 
	
		wait until DONE = '1';	  
		wait until clk'event and clk='0';
		
		read <=  '1' ;
		
		out_addr <= "01" ; 
		wait for ClkPeriod ; 
		hwrite(Vectorline, out_data); -- put std_logic_vector onto line variable
		writeline(out_vectorFile, VectorLine); -- write line variable onto output file
		
		out_addr <= "10" ; 
		wait for ClkPeriod ;  
		hwrite(Vectorline, out_data);
		writeline(out_vectorFile, VectorLine);
		
		out_addr <= "11" ; 
		wait for ClkPeriod ;   	  
		hwrite(Vectorline, out_data);
		writeline(out_vectorFile, VectorLine); 
		
		read <= '0';
		
		wait;
	
  end process;	   
  
  clk <= not clk after ClkPeriod/2;
  
end TB_ARCHITECTURE;