library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity minmaxavg is
	generic(
		n : INTEGER := 32; -- input bits
		k : INTEGER := 8;  -- number of values to be processed
		m : INTEGER := 3 );	-- log2k	
	 port(
		 clk : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 START : in STD_LOGIC;
		 write : in STD_LOGIC;
		 read : in STD_LOGIC;
		 in_data : in STD_LOGIC_VECTOR(n-1 downto 0);
		 in_addr : in STD_LOGIC_VECTOR(m-1 downto 0);
		 out_addr : in STD_LOGIC_VECTOR(1 downto 0);
		 DONE : out STD_LOGIC;
		 out_data : out STD_LOGIC_VECTOR(n-1 downto 0)
	     );
end minmaxavg;

architecture dataflow of minmaxavg is

	component controller
	port(
		clk : in std_logic;
		reset : in std_logic;
		START : in std_logic;
		ltMIN : in std_logic;
		gtMAX : in std_logic;
		zi : in std_logic;
		reg_reset : out std_logic;
		Esum : out std_logic;
		Emin : out std_logic;
		Emax : out std_logic;
		ECi : out std_logic;
		comp : out std_logic;
		DONE : out std_logic);
	end component;

	component datapath
	generic(
		n : INTEGER := 32;
		k : INTEGER := 8;
		m : INTEGER := 3);
	port(
		clk : in std_logic;
		in_data : in std_logic_vector(n-1 downto 0);
		in_addr : in std_logic_vector(m-1 downto 0);
		write : in std_logic;
		read : in std_logic;
		out_addr : in std_logic_vector(1 downto 0);
		reg_reset : in std_logic;
		Esum : in std_logic;
		Emin : in std_logic;
		Emax : in std_logic;
		ECi : in std_logic;
		comp : in std_logic;
		ltMIN : out std_logic;
		gtMAX : out std_logic;
		zi : out std_logic;
		out_data : out std_logic_vector(n-1 downto 0));
	end component;
 	
	signal ltMIN, gtMAX, zi: STD_LOGIC; -- from datapath to controller		 		 
	signal reg_reset, Esum, Emin, Emax, ECi, comp: STD_LOGIC; -- from controller to datapath
	
begin

    D1 : datapath
	generic map(
		n => n,
		k => k,
		m => m
	)
	port map(
		clk => clk,
		in_data => in_data,
		in_addr => in_addr,
		write => write,
		read => read,
		out_addr => out_addr,
		reg_reset => reg_reset,
		Esum => Esum,
		Emin => Emin,
		Emax => Emax,
		ECi => ECi,
		comp => comp,
		ltMIN => ltMIN,
		gtMAX => gtMAX,
		zi => zi,
		out_data => out_data
	);	

	C1 : controller
	port map(
		clk => clk,
		reset => reset,
		START => START,
		ltMIN => ltMIN,
		gtMAX => gtMAX,
		zi => zi,
		reg_reset => reg_reset,
		Esum => Esum,
		Emin => Emin,
		Emax => Emax,
		ECi => ECi,
		comp => comp,
		DONE => DONE
	);


end dataflow;