library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.std_logic_unsigned.all ; 
USE work.components.all ;

entity datapath is						  
	generic(
		n : INTEGER := 32; -- input bits
		k : INTEGER := 8;  -- number of values to be processed
		m : INTEGER := 3 );	-- log2k
	 port(
		 clk : in STD_LOGIC;
		 in_data : in STD_LOGIC_VECTOR(n-1 downto 0);
		 in_addr : in STD_LOGIC_VECTOR(m-1 downto 0);
		 write : in STD_LOGIC;
		 read : in STD_LOGIC;
		 out_addr : in STD_LOGIC_VECTOR(1 downto 0);
		 reg_reset, Esum, Emin, Emax, ECi, comp: in STD_LOGIC;
		 ltMIN, gtMAX, zi: out STD_LOGIC;
		 out_data : out STD_LOGIC_VECTOR(n-1 downto 0)
	     );
end datapath;

architecture dataflow of datapath is	 	
	constant inactive: std_logic := '0';
	signal ADATA 	: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
	signal SUM 		: STD_LOGIC_VECTOR(n+m-1 DOWNTO 0);
	signal NEW_SUM 	: STD_LOGIC_VECTOR(n+m-1 DOWNTO 0);  
	signal AVR 		: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
	signal MIN 		: STD_LOGIC_VECTOR(n-1 DOWNTO 0); 
	signal MAX 		: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
	signal OUT_MUX 	: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
	signal OUT_REG 	: STD_LOGIC_VECTOR(n-1 DOWNTO 0); 
	signal Zero 	: STD_LOGIC_VECTOR(n-1 DOWNTO 0); 
	signal ADDR		: STD_LOGIC_VECTOR(m-1 downto 0); 	  
	signal Ci		: STD_LOGIC_VECTOR(m-1 downto 0);  	
begin	  
	RegSUM: regne GENERIC MAP ( n => n+m )
	PORT MAP ( 	R => NEW_SUM ,
				rst => reg_reset,
				set => inactive,
				E => Esum, 
				clk => clk, 
				Q => SUM ) ;	 
				
	RegMIN: regne GENERIC MAP ( n => n )
	PORT MAP ( 	R => ADATA ,   
				rst => inactive,
				set => reg_reset, 
				E => Emin, 
				clk => clk, 
				Q => MIN ) ;
				
	RegMAX: regne GENERIC MAP ( n => n )
	PORT MAP ( 	R => ADATA ,
				rst => reg_reset, 	
				set => inactive,
				E => Emax, 
				clk => clk, 
				Q => MAX ) ;   
				 
	RegOUT: regne GENERIC MAP ( n => n )
	PORT MAP ( 	R => OUT_MUX ,
				rst => reg_reset, 
				set => inactive,
				E => read, 
				clk => clk, 
				Q => OUT_REG ) ;   

	Counter: upcount GENERIC MAP ( m => m )
		PORT MAP ( 	Reset => reg_reset, 
				clk => clk, 
				E => ECi,  
				Q => Ci ) ;	 

	Memory:	RAM_16Xn_DISTRIBUTED   
	GENERIC MAP ( n => n,
				  m => m)
	 PORT MAP (	  
	 	 CLK => clk,
		 WE => write,
		 ADDR => ADDR,
		 DATA_IN => in_data,
		 DATA_OUT => ADATA
	     ) ;  							  
	
	--counter and memory
	ADDR <= in_addr when comp='0' else Ci;
	
	Zi <= '1' when Ci = k-1 else '0';							 
		
	--max, min, and average computation
	NEW_SUM <= SUM + ADATA;
	
	AVR(n-1 downto 0) <= SUM(n+m-1 downto m);

	ltMIN <= '1' when ADATA < MIN else '0';
	
	gtMAX <= '1' when ADATA > MAX else '0';		
		
	Zero <= (OTHERS => '0');		   
	
	--output signals
	with out_addr select
	  OUT_MUX <= MIN WHEN "01",
				 MAX WHEN "10",
				 AVR WHEN "11",
				 Zero WHEN OTHERS ;
				 
	out_data <= OUT_REG when out_addr /= "00" else (OTHERS => 'Z') ;	  

end dataflow;