library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity controller is
	port(	
		 clk: in STD_LOGIC;
		 reset : in STD_LOGIC;
		 START : in STD_LOGIC; 
		 ltMIN, gtMAX, zi: in STD_LOGIC;		 		 
		 reg_reset, Esum, Emin, Emax, ECi, comp: out STD_LOGIC;
		 DONE : out STD_LOGIC
	     );
end controller;

architecture behavioral of controller is
	type state is (S1,S2,S3,S4);
	signal nx_state, pr_state: state;
begin	   
	process (clk,reset)
	begin		  
		IF (reset='1') THEN
			pr_state <= S1;
		ELSIF (clk'EVENT AND clk = '1') THEN
				pr_state <= nx_state;
		END IF;
	end process;
	
	process (pr_state,reset,START,zi)
	begin
		case pr_state is  
			when S1 => if START = '0' then nx_state <= S1 ; 
						else nx_state <= S2 ; end if ;
			when S2 => nx_state <= S3 ;  
			when S3 => if zi = '0' then nx_state <= S3 ; 
						else nx_state <= S4 ; end if ;	 
			when S4 => if reset = '1' then nx_state <= S1 ; 
						elsif START ='1' then nx_state<= S2 ;
						else nx_state <= S4 ; end if ;	
		end case ;
	end process ;	
	
	reg_reset <= '1' WHEN ( pr_state = S1 )  or ( pr_state = S2 ) ELSE '0';
	comp <= '1'  	WHEN pr_state = S3 	ELSE '0' ;	
	Esum <= '1'  	WHEN pr_state = S3 	ELSE '0' ;
	Emin <= ltMIN 	WHEN pr_state = S3 	ELSE '0' ; 
	Emax <= gtMAX 	WHEN pr_state = S3 	ELSE '0' ;
	DONE <= '1' 	WHEN pr_state = S4 	ELSE '0' ;	
	ECi <= '1' 		WHEN (pr_state = S3 and zi = '0' ) ELSE '0';

end behavioral;