LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

PACKAGE components IS

    COMPONENT regne  
         GENERIC ( n : INTEGER := 32 ) ;
			PORT (	R 	: IN 	STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
					rst : IN 	STD_LOGIC ;	
					set	: IN 	STD_LOGIC ;
					E 	: IN 	STD_LOGIC ;
					clk 	: IN 	STD_LOGIC ;
					Q 	: OUT 	STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
    END COMPONENT ;	 
	
	COMPONENT upcount  
    GENERIC ( m : INTEGER := 3 ) ;
	PORT ( 	Reset 		: IN 	STD_LOGIC ;
			clk		: IN 	STD_LOGIC ;
			E			: IN 	STD_LOGIC ;
			Q 			: OUT STD_LOGIC_VECTOR(m-1 downto 0 )) ;
   END COMPONENT ; 
   
   COMPONENT RAM_16Xn_DISTRIBUTED is	
	 GENERIC ( n : INTEGER := 32;
	 		   m : INTEGER := 3 ) ;
	 port(
		 CLK 		: in STD_LOGIC;
		 WE 		: in STD_LOGIC;
		 ADDR 		: in STD_LOGIC_VECTOR(m-1 downto 0);  
		 DATA_IN 	: in STD_LOGIC_VECTOR(n-1 downto 0);
		 DATA_OUT 	: out STD_LOGIC_VECTOR(n-1 downto 0)
	     );
   end COMPONENT ;	  
   
 END components ;