library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;


ENTITY RAM_16Xn_DISTRIBUTED is	
	GENERIC ( n : INTEGER := 32;
			  m : INTEGER := 3) ;
	 port(
		 clk 		: in STD_LOGIC;
		 WE 		: in STD_LOGIC;
		 ADDR 		: in STD_LOGIC_VECTOR(m-1 downto 0);  
		 DATA_IN 	: in STD_LOGIC_VECTOR(n-1 downto 0);
		 DATA_OUT 	: out STD_LOGIC_VECTOR(n-1 downto 0)
	     );
END RAM_16Xn_DISTRIBUTED;	 

architecture RAM_16Xn_INFERRED of RAM_16Xn_DISTRIBUTED is

type mem_type is array ((2**m)-1 downto 0) of std_logic_vector(n-1 downto 0);
signal mem:mem_type;

begin 			 

	DATA_OUT<=mem(conv_integer(ADDR));
	
	U_mem_write_1: process (CLK, WE, ADDR)
	BEGIN
		if (CLK'event and CLK='1') then
			if (WE='1') then
				mem(conv_integer(ADDR))<=DATA_IN;
			end if;
		end if;
	end process;
	 
end RAM_16Xn_INFERRED;