library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity shiftrne is		 
	 generic (N : integer := 2);
	 port(
		 clock : in STD_LOGIC;
		 l : in STD_LOGIC;
		 e : in STD_LOGIC;		
		 w: in STD_LOGIC;
		 data_in : in STD_LOGIC_VECTOR(N-1 downto 0);
		 q : out STD_LOGIC_VECTOR(N-1 downto 0)
	     );	

end shiftrne;
architecture behavioral of shiftrne is	
	signal qtemp: std_logic_vector(N-1 downto 0);
begin
	process(clock)
	begin
		if (clock'event and clock = '1') then
			if l = '1' then
				qtemp <= data_in ;
			elsif e = '1' then
				for i in 0 to N-2 loop
					qtemp(i) <= qtemp(i+1) ;
				end loop ;
				qtemp(n-1) <= w ;
			end if ;
		end if ;
	end process ;	
	q <= qtemp;
end behavioral ;