library IEEE;
use IEEE.STD_LOGIC_1164.all;	  
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity datapath is		 
	generic(N : integer:= 4;
			logN: integer:= 2) ;
	port(		   
		clock: in STD_LOGIC;
	 	data : in STD_LOGIC_VECTOR(N-1 downto 0);
	 	la: in STD_LOGIC;
		ea, lb, eb: in STD_LOGIC;
		z: out STD_LOGIC;
		a0: out STD_LOGIC;
		b: out STD_LOGIC_VECTOR(logN-1 downto 0)
	     );
end datapath;

architecture behavioral of datapath is	
	component upcount
	generic(
		N : INTEGER := 2);
	port(
		clock : in std_logic;
		l : in std_logic;
		e : in std_logic;
		data_in : in std_logic_vector(N-1 downto 0);
		q : out std_logic_vector(N-1 downto 0));
	end component;
	component shiftrne
	generic(
		N : INTEGER := 2);
	port(
		clock : in std_logic;
		l : in std_logic;
		e : in std_logic;
		w : in std_logic;
		data_in : in std_logic_vector(N-1 downto 0);
		q : out std_logic_vector(N-1 downto 0));
	end component;
	signal A: std_logic_vector(N-1 downto 0); -- internal wires in block diagram are signals
	signal zerotemp : std_logic_vector(logN-1 downto 0);
begin	   
	zerotemp <= (others => '0');
	shift1 : shiftrne
	generic map(N => N)
	port map(
		clock => clock, l => la, e => ea,
		w => '0', data_in => data, q => a );	 
	
	count1 : upcount
	generic map(N => logN)
	port map(
		clock => clock, l => lb, e => eb,
		data_in => zerotemp, q => b );		 

	z <= '1' when (conv_integer(unsigned(a)) = 0 ) else '0';	
	a0 <= a(0);

end behavioral;