library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity controller is
	 port(
	 	clock, resetn : in STD_LOGIC; 
	 	s: in STD_LOGIC;
	 	z,a0: in STD_LOGIC;
		ea,lb,eb: out STD_LOGIC;
		done: out STD_LOGIC
	     );
end controller;

architecture behavioral of controller  is
	type state is (S1, S2, S3);
	signal pr_state, nx_state: state;
begin
	-- section 1: fsm register
	process (resetn,clock)
	begin
		if (resetn='0') then
			pr_state <= S1;
		elsif (clock'event and clock='1') then
			pr_state <= nx_state;
		end if;
	end process;
	
	-- section 2: next state function
	next_state_function: process (s,z,pr_state)
	begin
		case pr_state is
			when S1 =>
				if (s = '0') then
					nx_state <= S1;
				else
					nx_state <= S2;
				end if;
			when S2 =>
				if (z = '0') then 
					nx_state <= S2;
				else
					nx_state <= S3;
				end if;		
			when S3 =>
				if (s = '0') then 
					nx_state <= S1;
				else
					nx_state <= S3;
				end if;		
			end case;
	end process;	
	
	--section 3: output function
	output_function: process (z,a0,pr_state)
	begin
		done <= '0'; ea <= '0'; lb <= '0'; eb <= '0'; -- set all outputs to zero by default
		case pr_state is
			when S1 => 
				lb <= '1';
			when S2 =>
				ea <= '1'; -- Moore type output before the IF statement
				if (z = '0' and a0 = '1') then 
					eb <= '1'; -- Mealy type output after the IF statement
				end if;
			when S3 => 
				done <= '1';
		end case;
	end process;
end behavioral;