library ieee;
use ieee.std_logic_1164.all;	
use ieee.std_logic_unsigned.all;
entity bitcount_tb is	  
	generic(N : integer := 8;  -- this is the value of N to be tested
	        logN: integer := 3); -- this is the value of logN to be tested
end bitcount_tb;
architecture TB_ARCHITECTURE of bitcount_tb is
	component bitcount	 
	 generic(N : integer:= 8;		-- comment this out for post-synthesis and post-place and route sims
			logN: integer:= 3) ;	-- comment this out for post-synthesis and post-place and route sims
	port(
		clock : in std_logic;
		resetn : in std_logic;
		la : in std_logic;
		s : in std_logic;
		data : in std_logic_vector(N-1 downto 0);
		b : out std_logic_vector(logN-1 downto 0);
		done : out std_logic );
	end component;
	signal clock : std_logic := '0'; -- set initial value to 0
	signal resetn : std_logic;
	signal la : std_logic;
	signal s : std_logic;
	signal data : std_logic_vector(N-1 downto 0);
	signal b : std_logic_vector(logN-1 downto 0);
	signal done : std_logic;	
	constant clockperiod : time := 20 ns ;
begin	
	UUT : bitcount 
	    generic map (N => N, logN => logN)	 -- comment this out for post-synthesis and post-place and route sims
		port map (
			clock => clock,
			resetn => resetn,
			la => la,
			s => s,
			data => data,
			b => b,
			done => done
		);
		
	process
	begin		 
		s <= '0';  
		la <= '0';
		resetn <= '0'; -- put system in reset
		wait until (clock'event and clock='0'); -- negedge of clock
		wait for (clockperiod*2); -- wait two more clock cycles 					
		resetn <= '1'; -- deassert reset
		wait for clockperiod;
		la <= '1'; -- load data into system
		data <= (others => '0');
		wait for clockperiod;
		la <= '0';
		s <= '1'; -- tell system to begin computation		  
		wait until done='1'; -- wait until done
		
	
		for i in 1 to 2**N-2 loop -- assume all 1's not possible, 2**N means 2 to the power of N
			wait until (clock'event and clock='0'); -- negedge of clock
			s <= '0';
			wait for clockperiod*3;
			la <= '1'; -- load data into system
			data <= data+1;
			wait for clockperiod;
			la <= '0';
			s <= '1'; -- tell system to begin computation		  		
			wait until done='1';
		end loop;
		wait; -- wait forever
	end process;		
	
	clock <= NOT clock after (clockperiod/2);
end TB_ARCHITECTURE;