---------------------------------------------------------------------------------------------------
--
-- Description : Test Bench for MLU
--
---------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MLU_TB is
end MLU_TB;

architecture MLU_TB_ARCHITECTURE of MLU_TB is
	-- Component declaration of the tested unit
	component mlu
	port(
		NEG_A : in std_logic;
		NEG_B : in std_logic;
		NEG_Y : in std_logic;
		A : in std_logic;
		B : in std_logic;
		L1 : in std_logic;
		L0 : in std_logic;
		Y : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal TEST_NEG_A : std_logic;
	signal TEST_NEG_B : std_logic;
	signal TEST_NEG_Y : std_logic;
	signal TEST_A : std_logic;
	signal TEST_B : std_logic;
	signal TEST_L1 : std_logic;
	signal TEST_L0 : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal TEST_Y : std_logic;	  
	signal TEST_AB: std_logic_vector(1 downto 0);
	signal TEST_SEL: std_logic_vector(1 downto 0);

begin

	-- Unit Under Test port map
	UUT : mlu
		port map (
			NEG_A => TEST_NEG_A,
			NEG_B => TEST_NEG_B,
			NEG_Y => TEST_NEG_Y,
			A => TEST_A,
			B => TEST_B,
			L1 => TEST_L1,
			L0 => TEST_L0,
			Y => TEST_Y
		);										  
		
	TEST_A<=TEST_AB(1);
	TEST_B<=TEST_AB(0);
	TEST_L1<=TEST_SEL(1);
	TEST_L0<=TEST_SEL(0);

TESTING: process
begin
	TEST_NEG_A<='0';
	TEST_NEG_B<='0';
	TEST_NEG_Y<='0';	   
	
	TEST_AB<="00";
	TEST_SEL<="00";
	
	for I in 0 to 3 loop
		for J in 0 to 3 loop
			wait for 10 ns;
			TEST_AB<=TEST_AB+"01";
		end loop;
		TEST_SEL<=TEST_SEL+"01";
	end loop;

--------------------------------------------------------
-- Inputs and Output Negated
--------------------------------------------------------
	TEST_NEG_A<='1';
	TEST_NEG_B<='1';
	TEST_NEG_Y<='1';	   
	
	TEST_AB<="00";
	TEST_SEL<="00";
	
	for I in 0 to 3 loop
		for J in 0 to 3 loop
			wait for 10 ns;
			TEST_AB<=TEST_AB+"01";
		end loop;
		TEST_SEL<=TEST_SEL+"01";
	end loop;	

----------------------------------------------------------
-- Outputs Negated
----------------------------------------------------------
	TEST_NEG_A<='0';
	TEST_NEG_B<='0';
	TEST_NEG_Y<='1';	   
	
	TEST_AB<="00";
	TEST_SEL<="00";
	
	for I in 0 to 3 loop
		for J in 0 to 3 loop
			wait for 10 ns;
			TEST_AB<=TEST_AB+"01";
		end loop;
		TEST_SEL<=TEST_SEL+"01";
	end loop;  

---------------------------------------------------------
-- Inputs Negated
---------------------------------------------------------
	
	TEST_NEG_A<='1';
	TEST_NEG_B<='1';
	TEST_NEG_Y<='0';	   
	
	TEST_AB<="00";
	TEST_SEL<="00";
	
	for I in 0 to 3 loop
		for J in 0 to 3 loop
			wait for 10 ns;
			TEST_AB<=TEST_AB+"01";
		end loop;
		TEST_SEL<=TEST_SEL+"01";
	end loop;
	wait;

end process TESTING;	
	
	
end MLU_TB_ARCHITECTURE;