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--
-- Description : Minimum Logic Unit
--
---------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MLU is
	 port(
		 NEG_A : in STD_LOGIC;
		 NEG_B : in STD_LOGIC;
		 NEG_Y : in STD_LOGIC;
		 A : in STD_LOGIC;
		 B : in STD_LOGIC;
		 L1 : in STD_LOGIC;
		 L0 : in STD_LOGIC;
		 Y : out STD_LOGIC
	     );
end MLU;

architecture MLU_DATAFLOW of MLU is			
signal A1 : STD_LOGIC;
signal B1 : STD_LOGIC;
signal Y1 : STD_LOGIC;
signal MUX_0 : STD_LOGIC;
signal MUX_1 : STD_LOGIC;
signal MUX_2 : STD_LOGIC;
signal MUX_3 : STD_LOGIC;
signal L : STD_LOGIC_VECTOR(1 downto 0);

begin
	A1<=not A when (NEG_A='1') else	
		A;
	B1<=not B when (NEG_B='1') else 
		B;
	Y<=not Y1 when (NEG_Y='1') else
		Y1;
		
	MUX_0<=A1 and B1;
	MUX_1<=A1 or B1;
	MUX_2<=A1 xor B1;
	MUX_3<=A1 xnor B1;

	L <= L1 & L0;
	
	with L select
		Y1<=MUX_0 when "00",
		    MUX_1 when "01",
		    MUX_2 when "10",
		    MUX_3 when others;
	
end MLU_DATAFLOW;