Hands-On Session 2

Hands-On Session 2 - FPGA Synthesis and Implementation

Background Reading and Design Flow

Xilinx ISE/Modelsim Users:

Overview and Help:

Xilinx ISE 9.1 Help

Xilinx ISE 9.1 Synthesis and Simulation Guide

Synthesis and Implementation:

Xilinx ISE 9.1 using Syplicity Synplify Pro Synthesis

Xilinx ISE 9.1 using Xilinx XST Synthesis

Xilinx ISE 9.1 Implementation

Aldec Active-HDL Users:

Overview and Help:

Aldec Active-HDL 7.2 SP2 Software Manual

Aldec Design Flow (you can click on the Synthesis graphic and Implementation graphic for more info)

Synthesis and Implementation:

Synplicity Synplify Pro Synthesis Options

Xilinx XST Synthesis Options

Xilinx ISE Implementation Options

Handout

FPGA Synthesis Handout (PDF)

Bit-Counter Block Diagram and Spec

Bit-Counter Diagram (from Lecture 3)

Bit-Counter VHDL Code

This code is slightly different from what is presented in class. In this code the bitcount.vhd module is generic (N, logN are generic) whereas in the lecture the bitcount.vhd module is fixed (N=8, logN=3). The testbench decides what final values N and logN should be. Right-click and select "Save Target As" to save to computer.

Counter

Bit-Counter Test Bench