ECE 545 - Digital System Design with VHDL
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| Date | Lecture | HW Due | Project Due |
| Tue, Aug 26 |
Lecture 1 - Introduction to VHDL |
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| Tue, Sep 2 |
Lecture 2 - Combinational Logic Review Hands-On Session 1 - VHDL Simulators |
HW1:Syntax Due (Tue, Sep 2) |
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| Tue, Sep 9 |
Lecture 3 - Sequential Logic Review and Algorithmic State Machines |
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| Tue, Sep 16 |
Lecture 4 - Algorithmic State Machines and Dataflow VHDL Coding |
HW2:ASM Due (Thu, Sep 18) |
Part1:Groups Due (Tue, Sep 16) |
| Tue, Sep 23 |
Lecture 5 - Behavioral VHDL Coding (for Synthesis), Structural VHDL Coding |
HW3:Comb Logic Due (Thu, Sep 25) |
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| Tue, Sep 30 |
Lecture 6 - Behavioral VHDL Coding (for Synthesis): Simple Finite State Machines and ASMs |
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| Tue, Oct 7 |
Lecture 7 - FPGA Devices and FPGA Design Flow Hands-On Session 2 - FPGA Synthesis and Implementation |
HW4:Seq Logic Due (Thu, Oct 9) |
Part2:Vectors,ASM Due (Tue, Oct 7) |
| Tue, Oct 14 |
NO CLASS - DUE TO COLUMBUS DAY |
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| Tue, Oct 21 |
Lecture 8 - Combinational Logic with Process Statements, Midterm Review |
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Part3:Block Diagrams Due (Tue, Oct 21) |
| Tue, Oct 28 |
MIDTERM Hands-On Session - Extra Help (Sat, Nov 1) |
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| Tue, Nov 4 |
Lecture 9 - Timing of Digital Systems, Advanced Testbenches |
HW5:ASM VHDL Due (Thu, Nov 6) |
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| Tue, Nov 11 |
Lecture 10 - Memories (RAM,ROM) |
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| Tue, Nov 18 |
Lecture 11 - Design Optimization |
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| Tue, Nov 25 |
Lecture 12 - Advanced VHDL Syntax, VHDL Modeling of Microprocessors |
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Part4:VHDL/Report Due (Tue, Nov 25) |
| Tue, Dec 2 |
Lecture 13 - VHDL Modeling of Microprocessors (cont'd), Final Review |
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| Tue, Dec 9 |
FINAL EXAM |
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