Homework 6

due Thursday, November 13, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard

Do not submit HW6. This homework is practice to help understand FIFOs for the project.


Reading

VERY helpful code for this homework can be found here: example FIFO code. This code has not been verified and may not be exactly correct, but it should give you an idea of how a FIFO operates.

Problems

Part 1: FIFO Design

Design a FIFO (First-In, First-Out memory) with the following entity declaration:

entity fifo is
GENERIC (
  DEPTH : integer := 64;
  LOG2DEPTH : integer := 6);
  N : integer := 8);
PORT (
  clock, reset: in std_logic;
  wr_en, rd_en: in std_logic;
  datain : in std_logic_vector(N-1 downto 0);
  dataout : out std_logic_vector(N-1 downto 0);
  fifo_full, fifo_empty : out std_logic);
END fifo;


The operation of the FIFO is as follows. The FIFO has DEPTH words, each word is N bits. For example, a FIFO can have DEPTH=64 words, each word being N=8 bits. The reset is asynchronous active high. When the reset is asserted, the FIFO memory is cleared and the fifo_empty flag goes to high.

WRITING TO THE FIFO:
wr_en is a synchronous signal. When wr_en = 1 that means at the next rising edge of the clock the data on the datain port is input into the FIFO. See the example waveform below for entering two data elements into the FIFO. As soon as the FIFO has something in memory, the fifo_empty signal is low. If all DEPTH slots of the memory are used up, then fifo_full becomes high.

READING FROM THE FIFO:
When rd_en = 1 the data that was "first in" is immediately available on the dataout port. This is similar to the read signal of an asynchronous RAM. At the next rising clock edge, if rd_en is still high then the internal read pointer moves to the next position. Thus, when rd_en = 1 again, the data that was "next in" (which is now considered as the "first in" sample) is output immediately onto the dataout port. When the last data held in the FIFO is output, then the FIFO is empty and the fifo_empty signal goes high again.

FIFO timing waveform (PPT)

WRITING AND READING TIMING:
The writing to the FIFO can take place separated in time (as shown in the waveform) or back-to-back. The reading from the FIFO can take place separated in time or back-to-back (as shown in the waveform). Your design should be able to handle all cases.

DESIGN HINTS:
The design should be a simple datapath-like block, i.e. do NOT decompose into datapath and controller, design an ASM, etc. As a helpful example of a FIFO design, look here: example FIFO code.

WHAT TO DESIGN:
Design the entity fifo in VHDL. You do NOT need to synthesize or implement your design with the CAD TOOLS.

Part 2: FIFO Testing

Create a testbench for the FIFO. Instantiate a FIFO such that DEPTH=16, and N=8 bits. Consider the file below, called hash_input.txt. It has four lines, each line represents an 8-bit data value in hexadecimal format. Thus it represents 32 bits of data.

INPUT FILE:
hash_input.txt

TESTBENCH OPERATION:
Your testbench should:

1) Reset the FIFO
2) Put the value "00100000" in binary (i.e. 20 in hex) into the FIFO. This value is 32 in decimal and represents the number of bits in the file. (Be sure to assert wr_en and put the data onto the datain bus at the negative edge of the clock.)
3) Open the file hash_input.txt (the exact file given above). Using a loop,
  a) put the first value in the file (i.e. AF) into FIFO
  b) put the next value in the file (i.e. 34) into the FIFO
  c) put the next value in the file (i.e. 14) into the FIFO
  d) put the last value in the file (i.e. B1) into the FIFO. The FIFO should now have five values: 20, AF, 34, 14, and B1 (in hex). Only five of the sixteen FIFO slots are occupied, so fifo_full remains low.
4) Wait 10 clock cycles
5) Using a loop,
  a) read the first value from the FIFO (i.e. 20 should appear on the dataout port).
  b) read the next value from the FIFO (i.e. AF should appear on the dataout port).
  c) read the next value from the FIFO (i.e. 34 should appear on the dataout port).
  d) read the next value from the FIFO (i.e. 14 should appear on the dataout port).
  e) read the last value from the FIFO (i.e. B1 should appear on the dataout port). The FIFO should now be empty and the fifo_empty signal should be high.

What to Submit

1) Submit your source VHDL code (and any code for components you may use) and your testbench VHDL code.
2) Submit hash_input.txt (the exact file above). This is so I can download your submitted code and run it immediately.
3) Submit your functional simulation waveform in .awf (Aldec) or .wlf (Modelsim) format. You only need to run functional simulation. You do NOT need to perform synthesis or implementation in this homework.

Relationship to the Project

This homework is designed to help you with your project. In your project, your testbech will instantiate an input FIFO component, an output FIFO component, and the hash function. You will use files similar to what is being done in this file. In particular you will load the input FIFO with the decimal value of 1536 or 3072 (i.e. padded message length). Then you will read from hash_input.txt to load the padded message data into the FIFO. After you hash function operates and puts the hash output into the output FIFO, you should compare the results in the output FIFO with those expected in hash_output.txt (you can do this in whatever manner makes sense to you).