Homework 5
due Thursday, November 6, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Reading
Xilinx
Spartan-3 FPGA Family: Complete Data Sheet
Module 1: Introduction
- Features
- Architectural Overview
Module 2: Functional Description
- CLB Overview
- Block RAM Overview
- Dedicated Multipliers
Volnei A. Pedroni, Circuit Design with VHDL
- Chapter 8, State Machines
Optional Reading (for students who need more background about basics of digital system design)
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd edition or 3rd edition
- Chapter 8, Synchronous Sequential Circuits (sections 8.1 - 8.5, 8.8)
Problems
Part 1: Count_Match
Using your VHDL code (or the solution VHDL code), to synthesize, implement, and test the count_match circuit from Homework 4 where N=7. Since you must synthesize the count_match.vhd entity, make sure you change the default generic value of the count_match entity to N=7.
Create a testbench called count_match_tb.vhd that tests the design for N=7. The testbench should first reset the system; then the reset should be deasserted. After the system is reset the testbench should set enable equal to high; run the design until you see the match flag go high at least twice. Make sure to change reset and en on the NEGATIVE edge of the clock (as discussed in class to avoid setup/hold time issues). You should perform functional simulation, post-synthesis (or post-translate) simulation, and post-place-and-route simulation.
Specifically, you should:
- Perform synthesis for Spartan 3. Assume N=7.
- Perform post-synthesis simulation if using Aldec (post-translate simulation if using Xilinx/Modelsim) at some reasonable clock frequency (i.e. 50 MHz).
- Generate netlist RTL schematic
- Perform implementation targeting the smallest device of the Xilinx Spartan 3 family
- Perform post-place-and-route timing simulation at some reasonable clock frequency (i.e. 50 MHz)
- Perform static timing analysis
What to Turn In:
Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below.
- All source codes, including test bench
- Create a text file called count_match_results.txt. In the text file, give a short summary of:
- A. Results after synthesis: #slices, #flip-flops, #LUTs, #block RAMs, maximum clock frequency, minimum period. If your synthesis tool only gives slices instead of LUTs (or vice-versa) after synthesis, just note this in your text file.
- B. Results after implementation: #slices, #flip-flops, #LUTs, #block RAMs, maximum clock frequency, minimum period
- Synthesis report
- Netlist rtl schematic
- Full implementation report(s)
- Static timing analysis report
- Waveforms from simulation before synthesis (in .awf format for Active HDL or .wlf format for ModelSim)
- Waveforms from simulation post-synthesis (in .awf format for Active HDL) or post-translate (in .wlf format for ModelSim)
- Waveforms from timing simulation post place-and-route (in .awf format for Active HDL or .wlf format for ModelSim)
Part 2: LogCalc
Using your ASM (or the solution ASM) from Homework 2, develop complete VHDL code for the floor(log2(DATA)) problem from Homework 2. Create the code for:
any components (counters, registers, etc.) and packages you use to create a structural design
datapath.vhd
controller.vhd
logcalc.vhd : the top-level entity. N, the number of bits of data, should be generic.
logcalc_tb.vhd : create a testbench which tests every value of DATA>1 for N=8, i.e. DATA =
00000001, 00000010, 00000011, etc.
The interface is on this ppt file: Interface
Simulate and verify the operation of logcalc_tb.vhd using Active HDL or ModelSim. Your simulation should run until the entire testbench is complete (i.e. your simulation should go through ALL possible values of DATA for N=8.)
Specifically, you should:
- Perform synthesis for Spartan 3. Assume N=8.
- Perform post-synthesis simulation if using Aldec (post-translate simulation if using Xilinx/Modelsim) at some reasonable clock frequency (i.e. 50 MHz)
- Generate netlist RTL schematic
- Perform implementation targeting the smallest device of the Xilinx Spartan 3 family
- Perform post-place-and-route timing simulation at some reasonable clock frequency (i.e. 50 MHz)
- Perform static timing analysis
What to Turn In:
Submit the following files using Blackboard. DO NOT submit your entire Aldec or Xilinx project with all its files, directories, subdirectories, temp files, etc.; only submit what is requested below.
- All source codes, including test bench
- Create a text file called logcalc_results.txt. In the text file, give a short summary of:
- A. Results after synthesis: #slices, #flip-flops, #LUTs, #block RAMs, maximum clock frequency, minimum period. If your synthesis tool only gives slices instead of LUTs (or vice-versa) after synthesis, just note this in your text file.
- B. Results after implementation: #slices, #flip-flops, #LUTs, #block RAMs, maximum clock frequency, minimum period
- Synthesis report
- Netlist rtl schematic
- Full implementation report(s)
- Static timing analysis report
- Waveforms from simulation before synthesis (in .awf format for Active HDL or .wlf format for ModelSim)
- Waveforms from simulation post-synthesis (in .awf format for Active HDL) or post-translate (in .wlf format for ModelSim)
- Waveforms from timing simulation post place-and-route (in .awf format for Active HDL or .wlf format for ModelSim)