Homework 4
due Thursday, October 9, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Reading
Volnei A. Pedroni, Circuit Design with VHDL
- Chapter 6, Sequential Code
- Chapter 10, Packages and Components
- Chapter 7.1, Constant
- Chapter 9.3, Carry Ripple and Carry Look Ahead Adders
Optional Reading (for students who need more background about basics of digital system design)
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd edition or 3rd edition
- Chapter 7, Flip-flops, Registers, Counters, and a Simple Processor (sections 7.1 - 7.13)
Problems
Part 1: Coding
Develop the following complete VHDL code including entity declarations, architectures, and testbenches
for circuits below:
- (1) Pedroni, Problem 10.3 (with modification): Carry Look Ahead Adder Constructed from Components.
Description: Create an unsigned carry lookahead adder with registered inputs and outputs, as shown in the figure here. All registers should have an asynchronous active-high reset. The top level entity should be called cla_adder.vhd and should have the input ports: reset, clock, cin, a (4-bit std_logic_vector), b (4-bit std_logic_vector), and should have the output ports: cout, s (4-bit std_logic_vector). Use components to build the design (i.e. create a PGU entity, a CLAU entity, a register entity or entities, etc.); you can use whatever hierarchy you want as long as it is component based. This is not an ASM problem, just a datapath coding problem. Do not do FPGA synthesis.
Testbench: Create a testbench called cla_adder_tb.vhd that tests the design. The testbench should first reset the system; then the reset should be deasserted. After the system is reset the testbench should hold b to a constant value, hold cin = 0, and sweep through all possible values of a. Then the test bench should hold cin = 1, keep b at the constant value, and sweep through all possible values of a again. All input data should change on the NEGATIVE edge of the clock (as discused in class to avoid setup/hold time issues).
- (2) Counter with Match Flag
Description: Create an entity called count_match.vhd as shown here. The N-bit generic unsigned counter has a synchronous active-high reset which causes the output q of the counter to be all zero's. It has a synchronous enable signal en. The output of the counter goes into a combinational logic block which checks to see if the output is equal to 2^N-3 and outputs a flag called match. For example, for N=3 bits, when the output is 101 (2^3-3=5 in decimal), match is high; for N=4 bits, when the output is 1101 (2^4-3=13 in decimal). The entity should have a generic port N (integer), the input ports: reset, en, clock, and the output port: match. You can choose to use hierarchy (component-based) or no hierachy in this problem. The code should work for any integer N (greater than or equal to 2). This is not an ASM problem, just a datapath coding problem. Do not do FPGA synthesis. The power sign in VHDL is **, i.e. 2^N = 2**N.
Testbench: Create a testbench called count_match_tb.vhd that tests the design for N=5. The testbench should first reset the system; then the reset should be deasserted. After the system is reset the testbench should set enable equal to high; run the design until you see the match flag go high at least twice. Make sure to change reset and en on the NEGATIVE edge of the clock (as discussed in class to avoid setup/hold time issues).
General remarks:
- Be sure to use std_logic or std_logic_vector for all entity input and output ports, not integer, signed, or unsigned. Use IN or OUT for port type; do not use BUFFER.
Part 2: Simulation
Simulate and verify the operation of all circuits using Active HDL or ModelSim.
Your simulation should run until the entire testbench is complete.
What to Turn In
Part 1: Coding
Turn in the following 4 files PLUS any additional files you have for other entities, packages, etc. you created. In the .vhd files, put your name as a comment near the top of each file. Submit all VHDL files using Blackboard.
cla_adder.vhd
cla_adder_tb.vhd
count_match.vhd
count_match_tb.vhd
Part 2: Simulation
Save the waveforms from simulation (i.e. in .awf format for Active HDL or .wlf format for ModelSim) and submit all of them using Blackboard.
Each filename should correspond with the test bench. For example, using Active HDL the counter with match flag waveform should be called count_match_tb.awf. Using ModelSim it should be called count_match_tb.wlf.