Homework 3
due Thursday, September 25, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Reading
Volnei A. Pedroni, Circuit Design with VHDL
- Chapter 4.1, Operators
- Chapter 5, Concurrent Code
Optional Reading (for students who need more background about basics of digital system design)
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd edition or 3rd edition
- Chapter 6, Combinational-Circuit Building Blocks
Problems
Part 1: Coding
Develop the following complete VHDL code including entity declarations, architectures, and testbenches
for circuits described in Pedroni, Circuit Design with VHDL:
- Problem 5.2 (part b only): Priority Encoder (using WHEN/ELSE)
- Problem 5.3: Simple Multiplier/Divider. Assume the inputs and outputs are unsigned. Assume a truncating division, i.e. 12/2=6 and 13/2=6. Note: use the correct number of output bits for each output.
- Problem 5.4: Unsigned Adder
- Problem 5.7: Simple Barrel Shifter
- Problem 5.8: Comparator
Remarks:
- Be sure to use std_logic or std_logic_vector for all entity input and output ports, not integer, signed, or unsigned. Use IN or OUT for port type; do not use BUFFER.
- Your testbench should go through ALL possible values (hint: use loops) of at least one data input and all control inputs (if a control input exists), while keeping the remaining data inputs constant.
- For the unsigned adder testbench, treat the carry-in signal like a "control" input (i.e. test the adder with carry-in set to '0' while sweeping one of the inputs and then test it with carry-in set to '1' while sweeping one of the inputs).
- ALL possible values means all possible patterns using '0' and '1'; you do not need to test 'X', 'L', 'H', etc.
Part 2: Simulation
Simulate and verify the operation of all circuits using Active HDL or ModelSim.
Your simulation should run until the entire testbench is complete (i.e. your simulation should go through ALL possible values of at least one data input and all control inputs, while keeping the remaining data inputs constant.)
What to Turn In
Part 1: Coding
Turn in the following 10 files. In the .vhd files, put your name as a comment near the top of each file. Submit all VHDL files using Blackboard.
pencoder.vhd
pencoder_tb.vhd
multdiv.vhd
multdiv_tb.vhd
adder.vhd
adder_tb.vhd
barrelshift.vhd
barrelshift_tb.vhd
comparator.vhd
comparator_tb.vhd
Part 2: Simulation
Save the waveforms from simulation (i.e. in .awf format for Active HDL or .wlf format for ModelSim) and submit all of them using Blackboard.
Each filename should correspond with the test bench. For example, using Active HDL the priority encoder waveform should be called pencoder_tb.awf. Using ModelSim it should be called pencoder_tb.wlf.