Homework 2
due Thursday, September 18, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Reading
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd edition or 3rd edition (from class handouts given on September 9)
- Section 8.10, Algorithmic State Machines
- Section 10.2.1, A Bit-Counting Circuit
- Section 10.2.2, ASM Chart Implied Timing Information
- Section 10.2.6, Sort Operation
Problems
Problem 1
Design a circuit that finds the floor(log2(DATA)) of a value DATA. DATA is an n-bit unsigned number that is greater than or equal to 1. (i.e. DATA is never zero). For example, if N=4 and DATA=4 in decimal, floor(log2("0100")) = 2. If N=4 and DATA=5 in decimal, floor(log2("0101")) = 2.
Use the same load methodology as in the bit-counting example in class to initially load the data; use the same done methodology as in the bit-counting example in class to tell the outside world the operation is complete. Hint: Your final datapath block diagram and detailed controller ASM should end up being somewhat similar to the bit-counting example.
The interface is on this ppt file: Interface
Design such a system using the following steps:
(1) Design the pseudocode for the algorithm.
(2) Create a high-level ASM of the design.
(3) Create the datapath block diagram of the design.
(4) Create the top-level interface diagram of design.
(5) Create the detailed controller ASM of the design.
Problem 2
In the sorting example presented in class and in the reading of section 10.6.2, the pseudocode uses two temporary registers (A and B) to implement the algorithm. It is possible to modify the algorithm so that it uses only one temporary register (A only).
Design such a system using the following steps:
(1) Design the pseudocode for the new algorithm which uses only one temporary register.
(2) Create a high-level ASM of the new design.
(3) Create the datapath block diagram of the new design.
(4) Create the top-level interface diagram of new design.
(5) Create the detailed controller ASM of the new design.
What to Turn In
This part of the homework does not involve VHDL code. You can either complete the homework using a drawing program (i.e. Visio, PowerPoint) or complete the homework by hand-drawing on paper. If you complete it using a drawing program, submit via Blackboard. If you complete it on paper, turn it in under my office door (ST2, Room 229) by the due date and time.
Turn in:
(1) Pseudocode
(2) High-level ASM
(3) Datapath block diagram
(4) Top-level interface diagram
(5) Detailed controller ASM
for both Problem 1 and Problem 2.