Homework 1
due Tuesday, September 2, 4:00 pm (NO LATE HOMEWORK ACCEPTED)
submission using Blackboard
Note: If you have problems with Blackboard, email your homework directly to the instructor by the due date. You should not need to use any CAD/FPGA tools for this assignment.
Reading
Volnei A. Pedroni, Circuit Design with VHDL
- Chapter 1, Introduction
- Chapter 2, Code Structure
- Chapter 3, Pre-Defined Data Types
Sundar Rajan, Essential VHDL: RTL Synthesis Done Right
Problems (5 points)
Pedroni, Circuit Design with VHDL:
- Problem 2.2 (part a only). Note the bottom gate is an OR gate, not an AND gate. Write the entire VHDL code (library, entity, and architecture).
- Problem 3.1
- Problem 3.2. Instead of using the assignments in table P3.2, use the assignments below. Determine which of the assignments below are legal and which are illegal. Briefly justify your answers. Also, determine the dimensionality of each assignment (on both sides).
x(2) <= a;
y(1,4) <= b;
y(1,5) <= x(0);
w(3) <= y(2,4);
x <= "10010010";
a <= "0111";
y(1)(2) <= w(1)(2);
y(7 downto 4) <= x(5 downto 3);
x(3) <= y(4,5);
w(3,2) <= '1';
- Problem 3.4. Create the architecture for the following entity.
Fill address 0 with data "1011", 1 with "1110", 2 with "0000", 3 with "0000",
4 with "0100", 5 with "1101", 6 with "1011", 7 with "1101":
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY rom_design IS
PORT (
address: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
output: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END rom_design;
- Problem 3.5. To simplify the problem, use the following entity declaration, i.e. a 4-bit output instead of a 5-bit output and ignore any overflow issues. I will discuss overflow issues and wordlength compatability in an upcoming lecture.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
ENTITY adder1 is
PORT (
a,b : IN STD_LOGIC_VECTOR(3 downto 0);
sum : OUT STD_LOGIC_VECTOR(3 downto 0));
END adder1;