ECE 545 - Digital System Design with VHDL
Fall 2008

Course Information

   Time and location: Tuesday, 4:30 - 7:10 PM, Krug Hall, Room 19
   Instructor: Dr. David Hwang
   Email: dhwang@gmu.edu
   Office Hours: Monday, 3:30 - 5:30 PM, Science and Tech II, Room 229
   TA: Shaunak Shah
   Email: sshahe@gmu.edu
   Office Hours: Monday, 1:30 - 3:30 PM, Science and Tech II, Room 203
    Thursday, 4:30 - 6:30 PM, Science and Tech I, Room 2B (2D)

Course Description

Introduces the design of complex digital systems using hardware description languages. Teaches design methodologies which partition a system into a datapath and controller. Focuses on synthesizable RTL VHDL code for digital circuit design using dataflow, structural, and behavioral coding styles. Introduces VHDL simulation and verification, and FPGA synthesis, placement, routing, timing analysis and performance optimization. Requires semester-long project devoted to the design of a complex digital system implemented on FPGAs.

Prerequisites: Graduate Standing. No official course prerequisite is required, but an undergraduate background in digital logic design is strongly recommended.

Required Textbooks

Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004, ISBN: 0-262-16224-5.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Supplementary Textbooks

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Edition, McGraw-Hill, 2008, ISBN: 0073529532. [Note: The 2nd edition of this book is also acceptable]

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd Edition, Morgan Kaufman, 2008, ISBN: 0120887851. [Note: The 2nd edition of this book is also acceptable]

Syllabus

Syllabus (PDF)

Class Schedule

Class Schedule (subject to modification)

Homework

Homework 1 (due Tuesday, September 2, 4:00 PM)

Homework 2 (due Thursday, September 18, 4:00 PM)

Homework 3 (due Thursday, September 25, 4:00 PM)

Homework 4 (due Thursday, October 9, 4:00 PM)

Homework 5 (due Thursday, November 6, 4:00 PM)

Homework 6 (due Thursday, November 13, 4:00 PM) Do not submit HW6. This homework is practice to help understand FIFOs for the project.

Project

Project Information (Project Part 4, due Tuesday, November 25, 4:00 PM)

Lectures

Note: for readability, I will post the PDF lectures as 2-slides per page instead of 3-slides per page. If you prefer 3-slides per page, open the PPT file, select "Print" and in the print menu select "Print What: Handouts" and "Slides Per Page: 3".

Lecture 1 - Introduction to VHDL (Printable Handouts: PDF)

Lecture 2 - Combinational Logic Review (Printable Handouts: PDF)

Lecture 3 - Sequential Logic Review and Algorithmic State Machines (Printable Handouts: PDF)

      Lecture 3 - Bit-Counting Example (Printable Handouts: PDF)

      Lecture 3 - Sorting Example (Printable Handouts: PDF)

Lecture 4 - Algorithmic State Machines and Dataflow VHDL Coding (Printable Handouts: PDF)

Lecture 5 - Behavioral VHDL Coding (for Synthesis), Structural VHDL Coding (Printable Handouts: PDF)

Lecture 6 - Behavioral VHDL Coding (for Synthesis): Simple Finite State Machines and ASMs (Printable Handouts: PDF)

Lecture 7 - FPGA Devices and Design Flow (Printable Handouts: PDF)

Lecture 8 - Combinational Logic with Process Statements, Midterm Review (Printable Handouts: PDF)

      Lecture 8 - Fall 2007 Midterm (solutions posted on Blackboard)

Lecture 9 - Timing of Digital Systems, Advanced Testbenches (Printable Handouts: PDF)

Lecture 10 - Memories (RAM/ROM) (Printable Handouts: PDF)

Lecture 11 - Design Optimization (Printable Handouts: PDF)

Lecture 12 - Advanced VHDL Syntax, VHDL Modeling of Microprocessors (Printable Handouts: PDF)

Lecture 13 - VHDL Modeling of Microprocessors (cont'd), Final Review (Printable Handouts: PDF)

      Lecture 13 - Fall 2007 Final (solutions will be sent via email)

Hands-On Sessions

Session 1 - VHDL Simulators

Session 2 - VHDL Synthesis and Implementation

Session 3 - VHDL Synthesis and Implementation (Additional Example)

Reference Material

Web page on type-casting in VHDL

 Explanation of ECE 545 CAD Tools

 ESA VHDL Modeling Guidelines (for reference only as an example of coding guidelines)

CAD Tool Tutorials

Aldec Active-HDL Tutorial Modules (from Aldec): Modules 1 through 6 of "HDL Design and Verification Lab".

Aldec Active-HDL Tutorial (from GMU ECE 332 Lab): pages 11 through 23.

Xilinx Modelsim Tutorial (using Modelsim SE/XE via the Xilinx ISE Interface, from Xilinx): pages 91 through 101.

VHDL Web Resources

VHDL Instructions: Templates and Examples

The Low Carb VHDL Tutorial