Hands-On Session 3 - FPGA Synthesis and Implementation Review
FPGA Synthesis and Implementation Brief Tutorial
Tutorial (PDF)
Min-Max-Avg Specification and Block Diagram
Min-Max-Avg Specification
Min-Max-Avg Block Diagram
Min-Max-Avg VHDL Code (in increasing hierarchical order)
Right-click and select "Save Target As" to save to computer.
Register with enable
Counter
Distributed RAM
Package of components
Datapath
Controller
Min-Max-Avg Top Level
Min-Max-Avg Testbench
Test vector input file