Bilal Habib

PhD Candidate

Welcome!

I am a Ph.D. student, under Prof. Kris Gaj at the GMU Electrical and Computer Engineering, in the Cryptographic Engineering Research Group (CERG).

Contact Information

  • E-mail: bhabib(at)masonlive.gmu.edu
  • Office: Room 3231 in Engineering Building II
  • Mailing address: 4400 University Drive, Farifax VA 22030, USA
  • Linkedin: My Profile

Education

Resume

Research Interests

  • Physical Unclonable Functions
  • Hardware Security
  • Embedded Systems
  • Efficient Implementation of Cryptographic Functions

Publications

    Journal:
  • Bilal Habib, Jens -Peter Kaps and Kris Gaj ."Implementation of Efficient SR-Latch PUF on FPGA and SoC devices," Journal of Microprocessors and Microsystems, 2016. (Under review).

  • Bilal Habib and Kris Gaj ."A Comprehensive Set of Schemes for PUF Response Generation," Journal of Microprocessors and Microsystems, 2016. (Under review).

    Conference:
  • Bilal Habib and Kris Gaj ." A Comprehensive Set of Schemes for PUF Response Generation," Proc. 12th International Symposium on Applied Reconfigurable Computing, Rio de Janeiro, Brazil, 22-24 March, 2016.[Link]
  • Bilal Habib, Jens -Peter Kaps and Kris Gaj ."Efficient SR-Latch PUF," Proc. 11th International Symposium on Applied Reconfigurable Computing, 2015, Bochum, Germany, April 15-17. 2015.[Link]
  • Bilal Habib, Kris Gaj and Jens -Peter Kaps ."FPGA PUF Based on Programmable LUT Delays," Proc. 16th EUROMICRO Conference on Digital System Design, 2013, Santander, Spain, Sep. 2013.[Link]
  • Bilal Habib, Ahmed Anber and Sultan Daud Khan. "The Effect of Multi-core Communication Architecture on System Performance ", Sixth International Symposium on Embedded Multicore SoCs, 20-22 September 2012, Aizu-Wakamatsu, Fukushima, Japan. [Link] [pdf]
  • Jens -Peter Kaps, Panasayya Yalla, Kishore K. Surapathi, Bilal Habib, Susheel Vadlamudi, and Smriti Gurung, "Lightweight Implementations of SHA-3 Finalists on FPGAs", Proc. 3rd SHA-3 Candidate Conf., Washington, D.C., Mar. 2012.[Link]
  • Jens -Peter Kaps, Panasayya Yalla, Kishore K. Surapathi, Bilal Habib, Susheel Vadlamudi, Smriti Gurung, and John Pham. "Lightweight implementations of SHA-3 candidates on FPGAs ", Progress in Cryptology - INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270-289, Dec, 2011. [Link]
  • Citations: Google Scholar

Projects

  • Design, Implementation and Analysis of Multi-core network on chip. Platform used: Virtex-5 FPGA
  • Characterization of FPGA devices for PUF. Devices used: Spartan-3, Spartan-6, Zynq
  • Designing low power Crypto cores for FPGA devices. Primary Target: Spartan-3
  • Designing high speed Crypto cores for FPGA devices. Primary Target: Spartan-3
  • 32-bit MIPS implementation. Platform used: Basys-2
  • Python based analysis tool for PUF. [Link]

Relevant Courses

  • Digital System Design with VHDL
  • Computer Arithmetic
  • VLSI Design for ASICs
  • Microprocessors
  • Cryptography and Computer Network Security
  • VLSI Test Concepts
  • High Performance Computing
  • Theory and Applications of Data Mining

Teaching Assistantship for Courses

  • ECE 447 Single-Chip Microcomputers Lab
  • ECE 445 Computer Organization
  • ECE 332 Digital Electronics and Logic Design Lab
  • ECE 280 Electric Circuit Analysis

Awards

  • Dissertation Completion Grant from the 'Office of Provost'. George Mason University.