Electrical Computer Engineering

Innovating the future

Book Chapter:
  • (Near-Threshold Computing) Avesta Sasan , Ahmed Eltawil, Fadi Kurdahi, Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance in Near-Threshold Computing - Technology, Methods, and Applications pp 57-73 Springer
Journal Publications:
  • (TNNLS 2019): Katayoun Neshatpour, Houman Homayoun, Avesta Sasan, ICNN: The Iterative Convolutional Neural Network, IEEE Transaction on Neural Network and Learning Systems (TNNLS), (2019 Submitted for Review)
  • (TVLSI 2019): Shervin Roshanisefat, Hadi M. Kamali, Avesta Sasan, SAT-hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain IEEE Transaction on VLSI (TVLSI), (2019 Submitted for Review), Impact Factor: 1.744
  • (TCHES 2019): Kimia Zamiri-Azar, Hadi M. Kamali, Houman Homayoun, Avesta Sasan, SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond The SAT Attacks Transaction of Cryptography Hardware and Embedded Systems, 2019, (Accepted for Pblication)
  • (JPDC 2018): Katayoun Neshatpour, Maria Malik, Avesta Sasan, Setareh Rafatirad, Tinoosh Mohsenin, Houman Homayoun, Energy-efficient acceleration of MapReduce applications using FPGAs Journal of Parallel and Distributed Computing, 2018, pp 119, 1-17, Impact Factor: 1.815
  • (TMSCS 2018): Katayoun Neshatpour, Maria Malik, Avesta Sasan, Setareh Rafatirad, Houman Homayoun, Hardware Accelerated Mappers for Hadoop MapReduce Streaming IEEE Transactions on Multi-Scale Computing Systems (2018) Impact Factor: 0.85
  • (TVLSI 2013): Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed Eltawil, Fadi Kurdahi, Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling, IEEE Trans. VLSI Syst. 20(4): 630-642 (2013), Impact Factor: 1.7
  • (TVLSI 2011): Houman Homayoun, Avesta Sasan, Alex V. Veidenbaum, Hsin C. Yao, Shahin Golshan, Payam Heydari, MZZ-HVS: Multiple sleep modes zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 2303-2316 (2011), Impact Factor: 1.7
  • (TVLSI 2011): Houman Homayoun, Avesta Sasan, Jean L. Gaudiot, Alex Veidenbaum, Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management, IEEE Transactions on VLSI Syst. 19(11): 2081-2094 (2011), Impact Factor: 1.7
  • (TVLSI 2011): Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation. IEEE Trans. VLSI Syst. 19(9): 1597-1609 (2011), Impact Factor: 1.7
  • (TVLSI 2008): Avesta Sasan, Ahmed Eltawil, Fadi Kurdahi, "A Low Power JPEG2000 Encoder With Iterative and Fault-Tolerant Error Concealment", IEEE transaction on TVLSI (2008), Impact Factor: 1.7
Conference Publications:
  • (ASP-DAC 2019): Ashkan Vakil, Houman Homayoun, Avesta Sasan, IR-ATA: IR Annotated Timing Analysis, A Flow for Closing the Loop Between PDN design, IR Analysis and Timing Closure, 24th Asia and South Pacific Design Automation Conference (ASP-DAC) (Accepted for publication) Acceptance Rate: ~25%
  • (DAC 2018): Hossein Sayadi, Nisarg Patel, Sai Manoj, Avesta Sasan, Setareh Rafatirad, Houman Homayoun, Ensemble Learning for Effective Run-Time Hardware-Based Malware Detection: A Comprehensive Analysis and Classification, Design Automation Conference (DAC) 2018: 1:1-1:6, Acceptance Rate: 22%
  • (DATE 2018): Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan, ICNN: An Iterative Implementation of Convolutional Neural Networks to Enable Energy and Computational Complexity Aware Dynamic Approximation. Design Automation and Test in Europe (DATE) 2018: 551-556, Acceptance Rate: 24%
  • (GLSVLSI 2018): Hadi M. Kamali, Avesta Sasan, MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture,.ACM Great Lakes Symposium on VLSI 2018: 459-462, Acceptance Rate: 27%
  • ( GLSVLSI 2018 ): Shervin Roshanisefat, Hadi M. Kamali, Avesta Sasan, SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware, ACM Great Lakes Symposium on VLSI 2018: 153-158, Acceptance Rate: 27%
  • (ISVLSI 2018): Hadi M. Kamali, Kimia Z. Azar, Kris Gaj, Houman Homayoun, Avesta Sasan, LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018: 405-410, Acceptance Rate: 30%
  • (IOLTS 2018): Shervin Roshanisefat, Harshith K. Thirumala, Kris Gaj, Houman Homayoun, Avesta Sasan, Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. IEEE international Symposium on On-Line Testing and Robust System Design (IOLTS) (2018)
  • (DAC 2017): Nisarg Patel, Avesta Sasan, Houman Homayoun, Analyzing Hardware Based Malware Detectors, Design Automation Conference (DAC) 2017: 25:1-25:6, Acceptance Rate: 22%
  • (ICCD 2017): Hossein Sayadi, Nisarg Patel, Avesta Sasan, Houman Homayoun, Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures, 37th IEEE International Conference on Computer Architecture Design (ICCD) 2017: 129-136, Acceptance Rate: 29%
  • (ISLPED 2017): Bhoopal Gunna, Lakshmi Bhamidipati, Houman Homayoun, Avesta Sasan, Spatial and Temporal Scheduling of Clock Arrival Times for IR Hot-Spot Mitigation, Reformulation of Peak Current Reduction,  ACM/IEEE International Symposium on Low Power Electronic and Design (ISLPED) 2017: 1-6, Acceptance Rate: 24%
  • (ISVLSI 2017): Lakshmi Bhamidipati, Bhoopal Gunna, Houman Homayoun, Avesta Sasan, A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews, IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017: 272-277, Acceptance Rate: 32%
  • (CODES+ISSS 2016): Katayoun Neshatpour, Avesta Sasan, Houman Homayoun, Big Data Analytics on Heterogeneous Accelerator Architectures, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2016: 16:1-16:3, Acceptance Rate: 23%
  • (ISCAS 2016): Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Big Biomedical Image Processing Hardware Acceleration: A Case Study for K-Means and Image Filtering, IEEE International Symposium on Circuit $ Systems (ISCAS) 2016: 1134-113, Acceptance Rate: Undisclosed
  • (ISPASS 2016): Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun, Characterizing Hadoop Applications on Microservers For Performance And Energy Efficiency Optimizations, IEEE International Conference on Performance Analysis of System and Software (ISPASS) , 2016, pp. 153-154, Acceptance Rate: 24%
  • (Big Data 2015): Maria Malik, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, System and Architecture Level Characterization of Big Data Applications on Big and Little Core Server Architectures, 2015 IEEE International Conference on Big Data (Big Data), 2015
  • (Big Data 2015): Katayoun Neshatpour, Maria Malik, Mohammad A. Ghodrat, Avesta Sasan and Houman Homayoun, "Energy-efficient acceleration of big data analytics applications using FPGAs," IEEE international Conference on Big Data (Big Data), 2015, pp. 115-123, Acceptance Rate: 17%
  • (ISQED 2012): Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi, History and Variation Trained Cache (HVT-Cache): A Process Variation Aware and Fine Grain Voltage Scalable Cache with Active Access History Monitoring, International Symposium on Quality Electronic Design (ISQED), 2012, pp. 498-505, Acceptance Rate: 36.3%
  • (CF 2010): Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt, Multiple Sleep Modes Leakage Control in Peripheral Circuits of All Major SRAM-based Processor Units, Conference of Computing Frontiers (CF), 2010, pp. 297-308
  • (HiPEAC 2010): Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt, RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor, High Performance and Embedded Architecture and Compilation (HiPEAC), 2010, pp. 216-231, Acceptance Rate: 25%
  • (CASES 2009): Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi, A Fault-Tolerant Cache Architecture for Sub-500mV Operation: Resizable Data Composer Cache (RDC-cache), International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2009, pp. 251-260, Acceptance Rate: 42%
  • (DATE 2009): Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi, Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling, Design Automation and Test in Europe (DATE), 2009, pp. 911-916, Acceptance Rate: 23%
  • (INCoS 2009): Mani Zarei, Amir M. Rahmani, Avesta Sasan, M. Teshnehlab, Fuzzy Based Trust Estimation for Congestion Control in Wireless Sensor Networks, International Conference on Intelligent Networking and Collaborative Systems (INCoS), 2009, pp. 233-239, Acceptance Rate: Undisclosed (28% in 2012)
  • (CASES 2008): Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors:, International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2008, pp. 197-206, Acceptance Rate: 33%
  • (DAC 2008): Houman Homayoun, Sudeep Pasricha, Avesta Sasan, Alexander V. Veidenbaum, Dynamic Register File Resizing and Frequency Scaling to Improve Embedded Processor Performance and Energy-Delay Efficiency, ACM/IEEE Design Automation Conference (DAC), 2008, pp. 68-71, Acceptance Rate: 23%
  • (ICCD 2008): Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, ZZ-HVS: Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits, IEEE International Conference on Computer Architecture Design (ICCD), 2008, pp. 699-706, Acceptance Rate: 34%
  • (LCTES 2008): Houman Homayoun, Sudeep Pasricha, Avesta Sasan, Alexander V. Veidenbaum, Improving Performance and Reducing Energy-Delay with Adaptive Resource Resizing for Out-of-Order Embedded Processors, ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)m 2008, pp. 71-78, Acceptance Rate: 25%
  • (ICSAMOS 2008): Avesta Sasan, Ahmed M. Eltawil, Fadi J. Kurdahi, Architectural and Algorithm Level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices, International Conference on Embedded Computer Systems: Architectural Modeling and Simulatioin (ICSAMOS), 2008, pp. 124-131, Acceptance Rate: 36%
  • (ICSAMOS 2008): Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum, A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation, International Conference on Embedded Computer Systems: Architectural Modeling and Simulatioin (ICSAMOS), 2008, pp. 195-202, Acceptance Rate: 36%
  • (DSD 2007): Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Avesta Sasan, Stanley Cheng, Error-Aware Design, Euromicro Symposium on Digital System Design (DSD), 2007, pp. 8-15, Acceptance Rate: Undisclosed
  • (ICCD 2007): Avesta Sasan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Limits on Voltage Scaling for Caches Utilizing Fault Tolerant Techniques, IEEE International Conference on Computer Architecture Design (ICCD), 2007, pp. 488-495, Acceptance Rate: 21%
  • (CEC 2006): Avesta Sasan, Kwei-Jay Lin, Solutions to a Complete Web Service Discovery and Composition, IEEE international Conference on E-Commerce (CEC), 2006, pp. 73-74, Acceptance Rate: Undisclosed

 

Student Walking on the Fairfax Campus