Electrical Computer Engineering

Innovating the future

Biography:

    Dr. Sasan received his B.Sc. in Computer Engineering from the University of California Irvine in 2005 with the highest honor (Summa Cum Laude). He then received his M.Sc. and his Ph.D. in Electrical and Computer Engineering from the University of California Irvine in 2006 and 2010 respectively. In 2010, Dr. Sasan joined the Office of CTO in Broadcom Co. working on the physical design and implementation of ARM processors, serving as physical designer, timing signoff specialist, and the lead of signal and power integrity signoff in this team. In 2014 Dr. Sasan was recruited by Qualcomm office of VLSI technology. In this role, Dr. Sasan developed different methodology and in-house EDAs for accurate signoff and analysis of hardened ASIC solutions. Dr. Sasan joined George Mason University in 2016, and he is currently serving as an Associate Professor in the Department of Electrical and Computer Engineering. Dr. Sasan research spans low power design and methodology, hardware security, accelerated computing, approximate computing, near-threshold computing, neuromorphic computing, and the Internet of Things (IoT) solutions.

Appointments:

  • George Mason University, Department of Electrical and Computer Engineering
    • Associate Professor, Present.
  • Qualcomm Co. VLSI technology team, San Diego CA.
    • Staff Engineer, 2014-2016.
  • Broadcom Co. Office of CTO, ARM Core Implementation team, Newport Beach, CA.
    • Sr. Staff Scientist, 2012-2014.
  • Broadcom Co. Office of CTO, ARM Core Implementation team, Newport Beach, CA.
    • Staff Scientist, 2010-2012.
  • Broadcom Co. Error Correcting Group, Newport Beach, CA.
    • Engineering Intern, 2008-2010,
  • Novelics Inc., Aliso Viejo, California, USA.
    • Contractor, 2007-2008
  • University of California Irvine, Department of Electrical and Computer Engineering
    • Research Assistant, 2005-2010.
  • Jazz Semiconductor, Newport Beach, California
    • Intern/part-time engineer, 2003-2007.

Education:

  • Ph.D. in Electrical and Computer Engineering
    • University of California Irvine, California, 2010
  • M.Sc. in Electrical and Computer Engineering
    • University of California Irvine, California, 2006
  • B.Sc. in Computer Engineering
    • University of California Irvine, California, 2005 (Summa Cum Laude)

Service:

  • (2020) Technical Program Committee
    • IEEE International Symposium on Hardware Oriented Security and Trust (HOST20)
  • (2019) Technical Program Committee
    • 1st Int. Workshop on Robust and Trustworthy Machine Learning 2019 (IWRTML)
  • (2019) Session Chair (Hardware Security)
    • 29th ACM Great Lakes Symposium on VLSI (GLSVLSI19)
  • (2019) Session Chair (Machine Learning)
    • 29th ACM Great Lakes Symposium on VLSI (GLSVLSI19)
  • (2019) Organizing Committee and Local Arrangement Chair
    • IEEE International Symposium on Hardware Oriented Security and Trust (HOST19)
  • (2019) Technical Program Committee
    • 29th ACM Great Lakes Symposium on VLSI (GLSVLSI19)
  • (2019) Technical Program Committee
    • 2019 International Conference on Reconfigurable computing and FPGAs (Reconfig19)
  • (2018) Technical Program Committee
    • 28th ACM Great Lakes Symposium on VLSI (GLSVLSI18)
  • (2018) Session Chair (Low Power Variation Aware Circuit Design)
    • 28th ACM Great Lakes Symposium on VLSI (GLSVLSI18)
  • (2018) Educational Proposal Review Panel Member
    • National Science Foundation, (NSF)
  • (2018) Research Proposal Review Panel Member
    • National Science Foundation (NSF)
  • (2018) Technical Program Committee
    • IEEE International Conference on Computer Design (ICCD18)
  • (2018) Panel Chair, Organizer and Moderator of Special Session, on Machine Learning
    • 28th ACM Great Lakes Symposium on VLSI (GLSVLSI18)
  • (2018) Organizing Committee and A/V Chair
    • IEEE International Symposium on Hardware Oriented Security and Trust (HOST18)
  • (2018) Reviewer
    • Transaction of Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • (2018) Technical Program Committee
    • International Test conference (Special Security Track) (ITC)
  • (2017) Research Proposal Review Panel
    • Member National Science Foundation (NSF)
  • (2017) Organizing Committee and A/V Chair
    • IEEE International Symposium on Hardware Oriented Security and Trust (HOST17)
  • (2017) Technical Program Committee
    • International Test conference (Special Security Track) (ITC)
  • (2017) Technical Program Committee
    • 27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
  • (2017) Technical Program Committee
    • IEEE International Conference on Computer Design (ICCD)
  • (2016) Industry Co-Panel Chair
    • IEEE Global Communication conference (GLOBECOM16)
  • (2016) Technical Program Committee
    • IEEE International Conference on Computer Design (ICCD)
  • (2016) Session Chair
    • Design Automation Conference (DAC)
  • (2016) Session Chair
    • Workshop on Cross layer SW/HW Optimization (UCI)
  • (2015) Technical Program Committee
    • 10th IEEE International Design and Test (IDT)
  • (2015) Technical Program Committee
    • IEEE International Conference on Computer Design (ICCD)

 

Student Walking on the Fairfax Campus